DSPIC33FJ128GP310T-I/PT - 16-bit 40 MIPS DSC 128KB Flash | Microchip
料号： DSPIC33FJ128GP310T-I/PT ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $8.42 | $8.42 |
| 10 | $7.58 | $75.80 |
| 100 | $6.74 | $674.00 |
| 500 | $6.06 | $3,030.00 |
| 1,000 | $5.46 | $5,460.00 |
DSPIC33FJ128GP310T-I/PT 概述
A digital signal controller (DSC) is a single-chip device that merges the control flow of a microcontroller with the mathematical throughput of a DSP. Within the power-management hierarchy of embedded systems, the dsPIC33F family sits between general-purpose PIC microcontrollers and dedicated DSPs, providing deterministic interrupt latency, hardware multiply-accumulate units, and rich peripherals on one die.
Key differentiators include the 16-bit modified Harvard architecture with DSP engine (single-cycle MAC, 40-bit accumulators), 128 KB of self-programmable FLASH, 85 general-purpose I/O on the 100-pin variant, and the industrial temperature range of -40C to +85C indicated by the I suffix. The /PT suffix identifies the 100-pin TQFP package in tape-and-reel delivery for automated assembly.
Architecturally, the device pairs a pipelined C compiler-friendly core with peripherals such as high-speed PWM, advanced analog (ADC), and serial interfaces (UART, SPI, I2C), enabling single-chip control of motor drives, power conversion, and precision sensing loops. The GP (General Purpose) subfamily emphasizes analog and communication peripherals over the motor-control-focused MC variants.
Typical applications include digital power supplies and PFC stages, sensor acquisition and signal-conditioning nodes, industrial automation controllers, and general embedded systems that benefit from DSP-grade math without a second processor.
When designing in this part, budget the 3.3V rail carefully: all I/O are 3.3 V only (5 V tolerance is absent in this family), and decoupling of every VDD/VSS pair plus the internal regulator capacitor is required per the manufacturer datasheet.
This page consolidates distributor stock signals, drop-in same-package alternatives, and practical design notes not found in the manufacturer datasheet alone.
直接替换替代料： DSPIC33FJ128GP310T-I/PT ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： DSPIC33FJ128GP310T-I/PT （相同外形与封装尺寸） ——差异在于 Package, Core Architecture, Programming Interface, Series, Packaging.
快速对比工具——选择替代料号进行并排对比：
DSPIC33FJ128GP310-I/PT
✅ 直接替换✓ 有现货
$4.4 / 个
查看数据手册 →DSPIC33FJ128GP310A-I/PT
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
DSPIC33FJ128GP310A-I/PF
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$5.7 / 个
查看数据手册 →DSPIC33FJ64GP310-I/PT
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$5.48 / 个
查看数据手册 →DSPIC33FJ256GP310-I/PT
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
DSPIC33FJ128GP306-I/PT
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$4.55 / 个
查看数据手册 →DSPIC33FJ128GP310T-I/PT 最大额定值与电气特性
| Core Architecture | 16-bit dsPIC33F RISC with DSP engine |
| Max CPU Speed | 40 MIPS |
| Program Memory (FLASH) | 128 KB (128K x 8) |
| RAM Size | 16 KB |
| 电源电压 | 3 V to 3.6 V |
| 工作温度 | -40C to +85C (Industrial) |
| 封装 | 100-TQFP (12x12 mm) |
| 安装类型 | Surface Mount |
| I/O Ports | 51 I/O available (package dependent) |
| Timers | General purpose timers per dsPIC33FJ family |
| Serial Interfaces | UART, SPI, I2C |
| Analog Peripherals | ADC (advanced analog, GP subfamily) |
| Packaging | Tape and Reel (T prefix) |
| RoHS 状态 | Compliant / Lead free |
| Programming Interface | ICSP (In-Circuit Serial Programming), 2-wire |
| Series | dsPIC33FJ128GP (General Purpose) |
DSPIC33FJ128GP310T-I/PT 100-tqfp (12x12 mm) 引脚配置指南
DSPIC33FJ128GP310T-I/PT（100-tqfp (12x12 mm) 封装）的引脚配置。 该数字 IC 包含 GPIO、通信接口（UART、SPI、I2C）和电源引脚。请参阅制造商数据手册以了解复用引脚功能和配置选项。对嵌入式系统设计和 PCB 布局至关重要。
暂无详细引脚数据： DSPIC33FJ128GP310T-I/PT.
请参阅 数据手册 以查看完整引脚配置。
典型应用
DSPIC33FJ128GP310T-I/PT 适用于 6 应用s: Digital Power Conversion, Industrial Automation Controllers, Sensor Acquisition and Signal Conditioning, Motor Drive Control, Embedded Communication Nodes, Test and Measurement Instrumentation.
Digital Power Conversion
The DSPIC33FJ128GP310T-I/PT's 40 MIPS core with single-cycle MAC and 40-bit accumulators executes current- and voltage-loop control mathematics fast enough for digital SMPS, PFC, and DC-DC stages. The dsPIC33FJ GP family high-speed PWM generates precisely timed switching edges, while the on-chip ADC samples feedback with low jitter. Placed as the sole supervisory controller, it replaces analog compensation networks with firmware, enabling adaptive gain scheduling and soft-start control. Designers must budget FLASH for compensator state machines and verify PWM resolution against switching frequency before layout freeze.
推荐
Industrial Automation Controllers
In factory automation nodes, the DSPIC33FJ128GP310T-I/PT combines 51 usable I/O, multiple UART/SPI/I2C ports, and 128 KB of self-programmable FLASH, letting one chip handle sensor polling, actuator drive, and fieldbus communication. The industrial -40C to +85C rating survives panel and machine-mount environments, and ICSP allows firmware field updates without desoldering. Its DSP engine accelerates filtering of noisy encoder and analog feedback signals. Consider the A-silicon variants to inherit errata corrections, and plan the 3.3 V-only I/O interfaces with level shifters where 5 V legacy peripherals are present.
推荐
Sensor Acquisition and Signal Conditioning
The GP (General Purpose) subfamily emphasizes advanced analog, making the DSPIC33FJ128GP310T-I/PT well suited for multi-channel data acquisition: the ADC digitizes sensor inputs while the DSP MAC engine runs FIR/IIR filters, RMS computations, and FFT-based analysis in real time at 40 MIPS. 128 KB FLASH retains calibration tables and logging buffers, and 16 KB RAM supports moderate buffering. UART or SPI streams results to a host. Designers should confirm exact ADC channel count and sampling rate in the family datasheet and keep analog routing away from the PWM pins for best noise performance.
推荐
Motor Drive Control
Although the MC subfamily is purpose-built for motors, the DSPIC33FJ128GP310T-I/PT still supports PWM-based drive of BLDC/PMSM stages up to moderate complexity, computing FOC-style transformations on its 40 MIPS DSP core. The 100-pin package exposes enough PWM and ADC pins for three-phase sensing. For demanding motor control with complementary PWM and dead-time hardware, designers should compare the DSPIC33EP64MC504 variants - same ecosystem and toolchain, motor-centric peripherals. Using the GP310 keeps PCB reuse across product lines sharing a common controller footprint and 3.3 V power architecture.
推荐
Embedded Communication Nodes
With multiple UART, SPI, and I2C peripherals on a single die, the DSPIC33FJ128GP310T-I/PT serves as protocol converters, gateways, and sensor-bus masters. The 40 MIPS core sustains line-rate UART throughput with CRC and framing computed in software, while DMA-free interrupt service is manageable given deterministic dsPIC33F interrupt latency. 128 KB FLASH accommodates stacked protocol stacks and OTA-style update loaders. Because I/O is strictly 3.0-3.6 V, RS-232/RS-485 transceivers must be 3.3 V-compatible or level-shifted; the ICSP port doubles as the field firmware channel.
推荐
Test and Measurement Instrumentation
Bench instruments and handheld meters benefit from the DSPIC33FJ128GP310T-I/PT's combination of 40 MIPS DSP math for RMS/THD computation, on-chip ADC for digitization, and generous I/O for keypad and display interfaces. The 100-pin TQFP gives layout flexibility to separate analog ground from digital switching, improving measurement resolution. Firmware fits comfortably in 128 KB FLASH including calibration and UI code. Battery-powered designs should exploit low-power idle/sleep states documented in the family reference manual, and the industrial temperature grade keeps specifications stable in field service environments.
推荐
推荐产品汇总
工程参考数据： DSPIC33FJ128GP310T-I/PT ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | DSPIC33FJ128GP310-I/PT | DSPIC33FJ128GP310A-I/PT | DSPIC33FJ64GP310-I/PT | DSPIC33FJ256GP310-I/PT |
|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 100-TQFP (12x12) | 100-TQFP (12x12) - same | 100-TQFP (12x12) - same | 100-TQFP (12x12) - same | 100-TQFP (12x12) - same |
| FLASH Program Memory | 128 KB | 128 KB | 128 KB | 64 KB | 256 KB |
| CPU Performance | 40 MIPS (16-bit) | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS |
| Supply Voltage | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V |
| Operating Temperature | -40C to +85C (I grade) | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Silicon Revision | Original (non-A) | Original | A revision (errata corrected) | Original | Original |
| Packaging Format | Tape & Reel | Tray | Tape & Reel | Tape & Reel | Tape & Reel |
| RoHS / Lead Free | Compliant / Yes | Compliant / Yes | Compliant / Yes | Compliant / Yes | Compliant / Yes |
关键差异点
- Errata-corrected A-silicon available in the same footprint （对比 DSPIC33FJ128GP310A-I/PT)
- FLASH scaling without PCB redesign （对比 DSPIC33FJ256GP310-I/PT)
- Tape-and-reel delivery for high-volume assembly （对比 DSPIC33FJ128GP310-I/PT)
设计说明
The dsPIC33FJ requires an external low-ESR capacitor (nominally 10 uF, ceramic) on the internal regulator output pin (VCAP/VDDCORE). Omitting it or using an undersized part causes brown-out resets and unreliable flash writes. Decouple every VDD/VSS pair with 0.1 uF ceramics placed within 2 mm of the pins, plus bulk 4.7-10 uF per power domain. Estimated: with typical 50 mA core + I/O current at 3.3 V, a 3.3 V rail regulator should be sized with at least 2x margin (100 mA) per controller.
All I/O on this family is 3.0-3.6 V only - there is no 5 V tolerance. Interfacing to 5 V sensors or legacy RS-232 logic requires level translators or 3.3 V-compatible transceivers. Keep the analog ADC inputs routed on a quiet island away from PWM and clock traces; use the dsPIC33F configuration bits to enable digital filtering where the peripheral supports it. For long SPI runs, series-terminate near the driver (22-33 ohm) to damp reflections.
Early non-A dsPIC33FJ silicon carries published errata affecting certain peripherals; check the Microchip errata sheet for your device revision and prefer the DSPIC33FJ128GP310A variants in new designs. Also verify oscillator configuration: the PLL multiplier settings must produce Fcy = Fosc/2 with Fosc <= 80 MHz (40 MIPS ceiling); out-of-range PLL configs simply fail to start. Reserve the ICSP pins (PGD/PGC/MCLR) on a header in production layouts - retrofitting debug access to a sealed 100-TQFP assembly is impractical.
合规信息
Distributor records (Infinity Electron, ABC Semi) state Lead free / RoHS Compliant. REACH and halogen-free status not stated in provided data - verify on Microchip's environmental compliance page.
