EP2AGX65CU1713N - Arria II GX FPGA 65K LE BGA-1713 | Altera
料号： EP2AGX65CU1713N ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $147.016 | $147.02 |
| 10 | $138.5 | $1,385.00 |
| 100 | $125 | $12,500.00 |
| 500 | $110 | $55,000.00 |
| 1,000 | $95 | $95,000.00 |
EP2AGX65CU1713N 概述
What is an FPGA? A Field-Programmable Gate Array (FPGA) is a semiconductor integrated circuit composed of configurable logic blocks (CLBs), programmable interconnect, programmable I/O, and dedicated hard-IP blocks such as transceivers, memory controllers, and DSP slices. The Arria II GX family belongs to the mid-range tier of Altera's FPGA portfolio, positioned below the high-end Stratix series and above the low-power Cyclone series, and optimized for cost-sensitive applications that still demand integrated transceivers and DSP capability.
Key features include 2,620 Kbit of embedded SRAM, 12 PLLs, 8 transceiver channels supporting data rates from 600 Mbps to 3.125 Gbps, hard IP for PCI Express Gen1 (x1, x4) and Gen2 (x1, x4), and dedicated 6x9-bit to 36x36-bit hardware multipliers for DSP. The device supports up to 612 user I/Os arranged across multiple I/O banks with LVDS, LVPECL, HSTL, SSTL, and LVCMOS standards. Configuration is supported via JTAG, AS, PS, and FPP modes, with on-chip 8-bit CRC and bitstream encryption (AES-128/256).
The Arria II GX architecture features dedicated transceiver physical coding sublayer (PCS) blocks, dynamic reconfiguration support via Partial Reconfiguration, and SignalTap II embedded logic analyzer capability. The 1713-ball BGA package uses flip-chip technology with a 40 mm x 40 mm body, providing high I/O count and excellent thermal performance.
Typical applications include wireless baseband processing, video broadcast equipment, industrial imaging, military radar signal processing, and PCI Express endpoint cards. The integrated transceivers make it particularly suitable for serial backplane interfaces, SRIO, CPRI, and Aurora protocol applications.
When designing with this device, pay close attention to transceiver reference clock jitter, PCB laminate selection for SerDes channels, and thermal management of the 1713-ball BGA. The BGA package requires X-ray inspection during PCB assembly.
This page synthesizes distributor pricing, drop-in alternatives from the Arria II GX family, and practical design notes that complement the manufacturer datasheet for procurement and engineering decisions.
直接替换替代料： EP2AGX65CU1713N ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EP2AGX65CU1713N （相同外形与封装尺寸） ——差异在于 Operating Temperature, Package, Logic Elements (LE), Transceiver Channels, Process Technology.
快速对比工具——选择替代料号进行并排对比：
EP2AGX65CU1717N
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
EP2AGX65CU1713G
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
EP2AGX65CU1713I
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
EP2AGX65CU1715N
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
EP2AGX65CU1713ES
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
EP2AGX65CU1713N 最大额定值与电气特性
| Family | Arria II GX |
| Logic Elements (LE) | 65,210 |
| Embedded Memory (bits) | 2,620,800 (2,560 Kb M9K + 130 Kb MLAB) |
| Multi-Gigabit Transceivers | 8 |
| Transceiver Data Rate | 600 Mbps to 3.125 Gbps |
| PLLs | 12 |
| Hardware Multipliers (18x18) | 312 |
| Maximum User I/O | 612 |
| PCI Express Hard IP | Yes (Gen1/Gen2 x1, x4) |
| Process Technology | 40 nm |
| 封装 | 1713-ball FCBGA, 40 mm x 40 mm |
| 工作温度 | 0C to +85C (commercial, suffix N) |
| Configuration | JTAG / AS / PS / FPP |
| Bitstream Encryption | AES-128 / AES-256 |
| RoHS 状态 | Compliant |
| 电源电压 | 0.9 V core / 1.1 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V (per bank) |
EP2AGX65CU1713N 1713-ball fcbga, 40 mm x 40 mm 引脚配置指南
EP2AGX65CU1713N（1713-ball fcbga, 40 mm x 40 mm 封装）的引脚配置。 该数字 IC 包含 GPIO、通信接口（UART、SPI、I2C）和电源引脚。请参阅制造商数据手册以了解复用引脚功能和配置选项。对嵌入式系统设计和 PCB 布局至关重要。
暂无详细引脚数据： EP2AGX65CU1713N.
请参阅 数据手册 以查看完整引脚配置。
典型应用
EP2AGX65CU1713N 适用于 6 应用s: Wireless Baseband Processing, Video Broadcast Equipment, PCI Express Endpoint Cards, Industrial Imaging and Machine Vision, Serial RapidIO Backplane Switching, Test and Measurement Instrumentation.
Wireless Baseband Processing
The EP2AGX65CU1713N's 8 multi-gigabit transceivers (up to 3.125 Gbps) and 312 18x18 hardware multipliers make it ideal for wireless baseband signal processing in LTE small cells and picocells. The 65k logic elements support wide datapath parallelism for FFT/iFFT engines and channel coding (Turbo/Viterbi/LDPC), while the 2,620 Kbit embedded memory enables sample buffering on-chip. Transceiver PCS hard IP supports CPRI and OBSAI protocols for direct connection to RF front-end cards. The 1713-ball BGA provides high I/O count for parallel antenna interface data and high-speed serial backhaul links.
推荐
Video Broadcast Equipment
The EP2AGX65CU1713N supports professional video broadcast applications including SDI (Serial Digital Interface) at 270 Mbps, HD-SDI at 1.485 Gbps, and 3G-SDI at 2.97 Gbps, all of which fit comfortably within the 3.125 Gbps transceiver capability. The 312 dedicated 18x18 multipliers accelerate video processing kernels such as deinterlacing, scaling, and color space conversion. The on-chip memory and 612 user I/Os enable simultaneous processing of multiple video streams. The 1713-ball BGA package's thermal performance is suitable for broadcast equipment chassis with forced-air cooling.
推荐
PCI Express Endpoint Cards
The EP2AGX65CU1713N integrates PCI Express Gen1 (x1, x4) and Gen2 (x1, x4) hard IP blocks, enabling direct implementation of PCIe endpoint cards without external PHY. The 8 transceivers can simultaneously drive PCIe x4 plus additional serial links such as SATA or Aurora. With 65k LE and 2,620 Kbit memory, the device accommodates DMA engines, descriptor processing, and protocol stack implementation. The 1713-ball BGA supports the lane and sideband signal count required for PCIe x4 plus reference clock, JTAG, and configuration pins.
推荐
Industrial Imaging and Machine Vision
The EP2AGX65CU1713N's 65k logic elements and 612 user I/Os are well-suited for multi-camera machine vision systems processing Camera Link, CoaXPress, or GigE Vision streams. The 8 transceivers support CoaXPress up to 3.125 Gbps per link, enabling connection of multiple high-resolution cameras. The 312 hardware multipliers accelerate image preprocessing such as Bayer demosaicing, color correction, and edge detection. Industrial temperature variants (I-suffix) of the same die extend deployment to factory floor environments. The 1713-ball BGA package provides robust thermal performance for continuous operation.
推荐
Serial RapidIO Backplane Switching
The EP2AGX65CU1713N's transceiver PCS supports Serial RapidIO (SRIO) at 1.25 Gbps, 2.5 Gbps, and 3.125 Gbps, making it suitable for embedded computing backplanes in military and aerospace systems. With 8 transceiver channels, the device can implement multi-port SRIO switches or endpoint bridging to PCIe and Aurora. The 65k logic elements handle packet processing, DMA, and protocol stack implementation. Hardware multipliers accelerate DSP preprocessing for radar or signal intelligence payloads sharing the same backplane.
推荐
Test and Measurement Instrumentation
The EP2AGX65CU1713N serves as a flexible processing core in test and measurement equipment such as protocol analyzers, logic analyzers, and high-speed digitizers. The 8 transceivers enable multi-lane data capture and generation across protocols (PCIe, USB 3.0, SRIO, SATA, custom). The 2,620 Kbit embedded memory provides deep sample buffer support, and the 312 hardware multipliers enable real-time DSP for trigger detection, pattern matching, and statistical analysis. SignalTap II logic analyzer hard IP allows internal signal visibility without external probing.
推荐
推荐产品汇总
工程参考数据： EP2AGX65CU1713N ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EP2AGX65CU1717N | EP2AGX65CU1713G | EP2AGX65CU1713I | EP2AGX65CU1715N | EP2AGX125EF35I5N |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) |
| Package | 1713-ball FCBGA (40x40 mm) | 1713-ball FCBGA (40x40 mm) | 1713-ball FCBGA (40x40 mm) | 1713-ball FCBGA (40x40 mm) | 1713-ball FCBGA (40x40 mm) | 1152-ball FCBGA - DIFFERENT |
| Logic Elements | 65,210 | 65,210 | 65,210 | 65,210 | 65,210 | 125,000 (+92%) |
| Transceivers | 8 (up to 3.125 Gbps) | 8 (up to 3.125 Gbps) | 8 (up to 3.125 Gbps) | 8 (up to 3.125 Gbps) | 8 (up to 3.125 Gbps) | 12 (+50%) |
| Embedded Memory | 2,620 Kbit | 2,620 Kbit | 2,620 Kbit | 2,620 Kbit | 2,620 Kbit | 5,140 Kbit (+96%) |
| Hardware Multipliers (18x18) | 312 | 312 | 312 | 312 | 312 | 576 (+85%) |
| Speed Grade | -3 (C3, slowest) | -7 (faster) | -3 (C3) | -3 (I3) | -5 (faster) | -5 |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | -40C to +100C (industrial) | 0C to +85C (commercial) | -40C to +100C (industrial) |
关键差异点
- Mid-range density with full transceiver capability in 1713-ball BGA （对比 EP2AGX45DF25C6N)
- Lower density but same 1713-ball footprint as higher-tier parts （对比 EP2AGX125EF35I5N)
- PCI Express hard IP eliminates external PHY cost （对比 Discrete PCIe implementation)
设计说明
The 1713-ball FCBGA package requires careful thermal management. Estimated: at full utilization (65k LE @ 100% toggle, 8 transceivers at 3.125 Gbps), total power dissipation may reach 10-15W. A multi-layer PCB with dedicated thermal vias under the BGA and forced-air cooling of at least 2 m/s airflow is recommended. Without thermal vias and a heatsink, junction temperature can exceed 100C under load. Refer to Altera's PowerPlay Early Power Estimator for design-specific thermal analysis.
PCB design for the 1713-ball FCBGA must use high-density interconnect (HDI) with microvia technology. The 1.0 mm ball pitch requires laser-drilled microvias in the top layers and stacked microvia structures for escape routing. Use a low-loss laminate (Df < 0.005 at 1 GHz) such as Megtron 6 or Rogers RO4350B for transceiver channels. Maintain 100 ohm differential impedance for SerDes pairs with length matching within 5 mils. X-ray inspection is mandatory after BGA assembly to verify solder joint integrity.
Transceiver channels require AC-coupled routing with 0.1 uF capacitors at the transmitter outputs per Altera reference design. Reference clock jitter must be kept below 0.7 ps RMS for 3.125 Gbps operation. Use a dedicated low-noise clock source such as a SiLabs Si530 or Skyworks SKY72310. Power supply decoupling requires 0.1 uF + 10 uF capacitors within 5 mm of each transceiver power pin, with ferrite beads separating analog and digital transceiver supplies.
Do not assume the 1713-ball BGA is pin-compatible with other Arria II GX packages - the EP2AGX65 is also offered in 780-ball and 1152-ball BGA packages with different pin assignments. When migrating between speed grades, re-run Quartus II timing analysis since Fmax differs between -3, -5, and -7 grades. Industrial temperature (I) suffix is mandatory for outdoor or industrial deployments; commercial (N) parts may fail outside 0C to +85C.
合规信息
RoHS and lead-free compliant per Altera/Intel PSG product declarations. NRND status per 2026-09-08 vendor information - not recommended for new designs but supported for existing customers.
