EP2C35F672C6 - Cyclone II FPGA 33K LE 672-FBGA | Intel
料号： EP2C35F672C6 ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $165 | $165.00 |
| 10 | $145 | $1,450.00 |
| 100 | $122 | $12,200.00 |
| 500 | $108 | $54,000.00 |
| 1,000 | $95 | $95,000.00 |
EP2C35F672C6 概述
A Cyclone II FPGA is a SRAM-based programmable logic device that allows designers to implement custom digital logic, signal processing, and embedded processor subsystems after PCB fabrication. It belongs to the broader category of programmable logic devices (PLDs), sitting alongside CPLDs, FPGAs, and structured ASICs. Compared with its predecessor Cyclone I, the Cyclone II family roughly doubled logic density while targeting the same low-power, high-volume end of the market.
Key features include 33,216 LEs, 483,840 total RAM bits distributed across M4K memory blocks, 70 embedded 18x18 multipliers for DSP operations, four PLLs with multiple output taps, and 475 user I/O pins. The device supports common I/O standards including LVTTL, LVCMOS, PCI, SSTL, and LVDS, with per-pin programmable drive strength and slew-rate control.
Cyclone II uses a 90 nm process node with a 1.2 V core supply and offers dedicated hardware multipliers and M4K block RAM that allow efficient implementation of FIR filters, FFTs, video pipelines, and embedded Nios II soft processors. The part number suffix indicates the C6 speed grade (commercial temperature range, approximately -40C to +85C ambient).
Typical applications include industrial motor control, video processing and surveillance, telecommunications line cards, embedded industrial controllers, and educational/development platforms. The high I/O count (475) and large memory (483 Kbits) make it well suited for parallel bus interfacing and data-pipeline processing.
When designing with the EP2C35F672C6, engineers should plan the power distribution network carefully: Cyclone II requires multiple supply rails (VCCINT, VCCA, VCCIO per bank) and the 672-ball FBGA demands a multilayer PCB with microvia technology. Use the Quartus II design software for synthesis, place-and-route, and timing closure.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers an actionable reference beyond what Altera/Intel provides in their legacy Cyclone II handbook.
直接替换替代料： EP2C35F672C6 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EP2C35F672C6 （相同外形与封装尺寸） ——差异在于 Process Technology, RoHS Status, Package, Speed Grade, Mounting Type.
快速对比工具——选择替代料号进行并排对比：
EP2C35F672C7
✅ 直接替换✓ 有现货
$119.95 / 个
查看数据手册 →EP2C35F672C8
✅ 直接替换✓ 有现货
$71.85 / 个
查看数据手册 →EP2C35F672I6
✅ 直接替换📋 参考替代料（不在目录中）
EP2C35F672C6N
✅ 直接替换✓ 有现货
$122.5 / 个
查看数据手册 →EP2C35F672I7N
✅ 直接替换📋 参考替代料（不在目录中）
EP2C35F672C6 最大额定值与电气特性
| Family | Cyclone II |
| Logic Elements (LE) | 33,216 |
| Total RAM Bits | 483,840 |
| Number of I/O | 475 |
| Number of Logic Array Blocks (LABs) | 2,076 |
| Embedded Multipliers (18x18) | 70 |
| Number of PLLs | 4 |
| Supply Voltage - Core | 1.15 V to 1.25 V |
| 工作温度 | 0C to +85C (commercial) |
| Speed Grade | C6 |
| 封装 / 外壳 | 672-BGA (FBGA) |
| 安装类型 | Surface Mount |
| Process Technology | 90 nm CMOS |
EP2C35F672C6 672-bga (fbga) 引脚配置指南
EP2C35F672C6（672-bga (fbga) 封装）的引脚配置。 该数字 IC 包含 GPIO、通信接口（UART、SPI、I2C）和电源引脚。请参阅制造商数据手册以了解复用引脚功能和配置选项。对嵌入式系统设计和 PCB 布局至关重要。
暂无详细引脚数据： EP2C35F672C6.
请参阅 数据手册 以查看完整引脚配置。
典型应用
EP2C35F672C6 适用于 6 应用s: Industrial Motor Control, Video Processing and Surveillance, Telecommunications Line Cards, Embedded Industrial Controllers, Educational and Development Platforms, Custom DSP and Audio Pipelines.
Industrial Motor Control
The EP2C35F672C6 with 33,216 logic elements and 70 hardware 18x18 multipliers can implement multi-axis motor control loops including field-oriented control (FOC) algorithms, encoder decoding, and over-current protection logic. The 475 user I/O pins support parallel connection to multiple PWM outputs, quadrature encoder inputs, Hall-effect sensors, and CAN/RS-485 comms peripherals. Cyclone II's 90 nm process allows up to 260 MHz operation, sufficient for 50 kHz torque-loop updates with oversampling. The four PLLs generate independent clocks for control loops and serial buses, while the 483 Kbit on-chip RAM buffers current/torque feedback data without external SRAM access.
推荐
Video Processing and Surveillance
With 483 Kbits of M4K block RAM and 70 hardware multipliers, the EP2C35F672C6 can implement real-time video pipelines including RGB-to-YCbCr conversion, 2D filtering, and motion detection for surveillance camera designs. The 475 I/Os can interface directly to DDR SDRAM, CMOS image sensors, and HDMI/LVDS display panels without external bridges. Designers can integrate a Nios II soft processor for camera control and TCP/IP offload. The 672-FBGA package provides sufficient I/O to drive two simultaneous 720p60 streams at 1.2 V core, all powered by a single 1.2 V regulator + multiple VCCIO banks.
推荐
Telecommunications Line Cards
The EP2C35F672C6 is well suited to telecommunications line-card applications because of its 475 user I/O count, four PLLs, and PCI/LVDS signalling support. Engineers can implement TDM switching fabrics, HDLC controllers, and hardware-accelerated protocol stacks on-chip, replacing multiple ASICs and CPLDs. Cyclone II's high I/O count allows direct parallel interconnect to T1/E1 framers, network processors, and bus crossbar switches, while the 483 Kbit RAM block provides frame-buffer memory for up to several thousand packets at line rate.
推荐
Embedded Industrial Controllers
The EP2C35F672C6 paired with a Nios II/f soft processor delivers an embedded controller capable of running industrial protocols like Modbus, Profibus slave, and EtherCAT slave controllers from open-source stacks. The 33,216 logic elements implement dual redundant CAN controllers, multi-channel ADC sequencer logic, and pulse-train output (PTO) for stepper-motor profiles. The 672-FBGA package offers sufficient I/O to drive 16 digital inputs, 16 digital outputs, RS-485 ports, and Ethernet MII bus to a PHY from a single device.
推荐
Educational and Development Platforms
The Cyclone II family, including the EP2C35F672C6, became the de-facto FPGA for university and training labs because it is well supported by Quartus II (free Web Edition), DE2-115 development boards, and decades of open teaching materials. The device fits comfortably within typical lab designs: UART bridges, VGA generators, custom CPU cores, RISC-V/8051 implementations, and pipeline educational examples. The 483 Kbit RAM is enough for on-chip cache and frame-buffer demos, while 475 I/O expose students to nearly every low-speed signalling standard.
推荐
Custom DSP and Audio Pipelines
With 70 hardware 18x18 multipliers, the EP2C35F672C6 can implement multi-channel audio processing pipelines including 32-tap equalizers, parametric EQ, dynamics compressors, and FFT-based spectral analysers at sample rates up to 192 kHz. The M4K RAM blocks provide coefficient storage and ring-buffer delay lines without off-chip memory. The four PLLs generate independent clocks for I2S, S/PDIF, and USB audio interfaces, while 475 I/Os drive multi-channel CODEC data buses, GPIO, and external LCD character displays in studio gear.
推荐
推荐产品汇总
工程参考数据： EP2C35F672C6 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EP2C35F672C7 | EP2C35F672C8 | EP2C35F672I6 | EP2C35F672C6N | EP2C35F672I7N | EP2C35F484I8N |
|---|---|---|---|---|---|---|---|
| Package | 672-FBGA | 672-FBGA (same) | 672-FBGA (same) | 672-FBGA (same) | 672-FBGA (same) | 672-FBGA (same) | 484-FBGA (different) |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 33,216 | 33,216 (same die) | 33,216 (same die) | 33,216 (same die) | 33,216 (same die) | 33,216 (same die) | 33,216 (same die) |
| Total RAM Bits | 483,840 | 483,840 | 483,840 | 483,840 | 483,840 | 483,840 | 483,840 |
| User I/O | 475 | 475 | 475 | 475 | 475 | 475 | 322 |
| Speed Grade | C6 (commercial) | C7 (slower) | C8 (faster) | I6 (industrial) | C6 (commercial, lead-free) | I7 (industrial) | I8 (industrial) |
| Multipliers (18x18) | 70 | 70 | 70 | 70 | 70 | 70 | 70 |
| Number of PLLs | 4 | 4 | 4 | 4 | 4 | 4 | 4 |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | -40C to +100C (industrial) | 0C to +85C (commercial) | -40C to +100C (industrial) | -40C to +100C (industrial) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND | NRND |
关键差异点
- Highest-density Cyclone II device in the standard product tier （对比 EP2C20F484I8N)
- Commercial temperature speed grade C6 （对比 EP2C35F672I6)
- 672-ball FBGA with 475 user I/O （对比 EP2C35F484I8N)
设计说明
The 672-ball FBGA package uses 1.0 mm ball pitch and a 27 mm x 27 mm body, requiring a multilayer PCB (typically 6+ layers) with laser-drilled microvias for breakout. Allocate at least 4 dedicated signal layers for the inner ball escape pattern, and keep a continuous ground plane beneath the device to control impedance and supply return paths. Use the Cyclone II FBGA-672 pin table from the Cyclone II Handbook (CII51007) when generating the PCB symbol.
Cyclone II requires three independent supply domains: VCCINT (1.15 V to 1.25 V core), VCCA (2.5 V analog supply for PLLs), and per-bank VCCIO (1.5 V, 1.8 V, 2.5 V, or 3.3 V depending on I/O standard). Decouple each VCCINT pin locally with a 0.1 uF X7R plus a 10 uF tantalum or polymer bulk cap; bulk VCCINT should supply at least 3 A transient for the C6 speed grade at high toggle rates. Power sequencing must follow the Cyclone II datasheet: VCCINT ramps first, then VCCA, then VCCIO banks.
Configuration mode selection (AS, PS, JTAG) must match the chosen configuration memory device. Common mistakes include selecting the wrong MSEL[2:0] pins for the configuration scheme, omitting the pull-up on nCONFIG, and not providing a 2.5 V reference for configuration EEPROM sharing. Plan the configuration clock source and CONF_DONE / nSTATUS pull-ups explicitly on the schematic rather than relying on defaults.
Estimated: At maximum toggle rates the EP2C35F672C6 core can draw up to 1.5 A from VCCINT, corresponding to roughly 1.9 W core dissipation. Combined with I/O bank power, total board dissipation may approach 3 W under worst-case conditions. With 4 thermal balls exposed to the package bottom, use 4 thermal vias per ball to an internal ground plane for heat spreading; aim for 1 sq-in of copper pad per ball in the BGA footprint.
合规信息
RoHS and lead-free status for EP2C35F672C6 marked unknown because the verified web data does not explicitly state compliance. Cyclone II commercial FPGAs in FBGA packages are typically lead-free per Intel legacy documentation, but engineers must verify with the actual device marking before assuming RoHS compliance for production designs.
