EP2S90F1020I4GA - 90K LEs Stratix II FPGA, 758 I/O FBGA-1020 | Intel
料号： EP2S90F1020I4GA ⚠ 最后一次采购| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $320 | $320.00 |
| 10 | $295 | $2,950.00 |
| 100 | $265 | $26,500.00 |
| 500 | $240 | $120,000.00 |
| 1,000 | $220 | $220,000.00 |
EP2S90F1020I4GA 概述
A Field Programmable Gate Array (FPGA) is a semiconductor device containing a matrix of configurable logic blocks (CLBs), programmable interconnect, and dedicated hardware blocks such as block RAM, DSP slices, and high-speed transceivers. Designers describe logic using HDL (Verilog or VHDL) and synthesize it onto the FPGA fabric, allowing rapid iteration versus ASIC development. FPGAs sit hierarchically between general-purpose microcontrollers and ASICs, offering higher performance-per-watt than CPUs for parallel workloads while preserving reprogrammability. The Stratix II family extends this to ASIC-prototyping and signal-processing designs with embedded multipliers and substantial block RAM.
Key features of the EP2S90 include up to 758 user I/O pins via the FBGA-1020 package, four enhanced phase-locked loops (PLLs) for clock management, support for external memory interfaces including DDR/DDR2/QDRII, and configuration via passive serial, fast passive parallel, or JTAG modes. The 'GA' suffix on the part number indicates the specific package and lead-free/RoHS designation as used by Altera/Intel ordering codes. The I4 speed grade places this part in the mid-performance Stratix II tier.
Architecturally, the Stratix II device uses an ALM-based logic structure with adaptive look-up tables, dedicated carry chains, and on-chip memory distributed across M512, M4K, and M-RAM blocks. The embedded DSP blocks implement 18x18 multipliers with optional accumulation and pre-adders, ideal for FIR filters and FFTs in wireless baseband and video processing pipelines.
Typical applications include ASIC prototyping, high-speed digital signal processing, telecom line cards, test and measurement equipment, and high-performance industrial control. When designing with this part, plan power sequencing carefully: the Stratix II requires multiple supply rails (VCCINT, VCCA, VCCIO, VCCPD) with monotonic ramp requirements and a specific POR (power-on-reset) sequence to avoid configuration failure.
直接替换替代料： EP2S90F1020I4GA ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EP2S90F1020I4GA （相同外形与封装尺寸） ——差异在于 Package, Speed Grade, Operating Temperature, Mounting Type, Process Technology.
快速对比工具——选择替代料号进行并排对比：
EP2S90F1020I4
✅ 直接替换✓ 有现货
$2200 / 个
查看数据手册 →EP2S90F1020I3N
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联系询价
查看数据手册 →EP2S90F1020C5N
✅ 直接替换✓ 有现货
$1240 / 个
查看数据手册 →EP2S90F1020C4N
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$1320 / 个
查看数据手册 →EP2S90F1020C3N
✅ 直接替换✓ 有现货
$1995 / 个
查看数据手册 →EP2S90F1020I4GA 最大额定值与电气特性
| Family | Stratix II |
| Logic Elements (LEs) | 90,960 |
| Embedded Memory | 4,520,488 bits (approximately 4.4 Mbit) |
| Embedded 18x18 Multipliers | 192 |
| Maximum User I/O | 758 |
| Process Technology | 90 nm CMOS |
| 封装 | 1020-ball FC-FBGA |
| 工作温度 | -40C to +100C (industrial) |
| Speed Grade | I4 (mid-performance, industrial) |
| Supply Voltage - Core (VCCINT) | 1.2 V nominal |
| Configuration Modes | Passive Serial, Fast Passive Parallel, JTAG |
| PLLs | 4 enhanced PLLs |
| External Memory Support | DDR, DDR2, QDRII, SDR |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant |
| Program Memory Type | SRAM (volatile, requires configuration device) |
EP2S90F1020I4GA 1020-ball fc-fbga 引脚配置指南
EP2S90F1020I4GA（1020-ball fc-fbga 封装）的引脚配置。 该数字 IC 包含 GPIO、通信接口（UART、SPI、I2C）和电源引脚。请参阅制造商数据手册以了解复用引脚功能和配置选项。对嵌入式系统设计和 PCB 布局至关重要。
暂无详细引脚数据： EP2S90F1020I4GA.
请参阅 数据手册 以查看完整引脚配置。
典型应用
EP2S90F1020I4GA 适用于 6 应用s: ASIC Prototyping, High-Speed Digital Signal Processing, Telecom Line Cards, Test and Measurement Instrumentation, Industrial Control and Automation, Military and Aerospace (Legacy Designs).
ASIC Prototyping
The EP2S90F1020I4GA's 90,960 LEs and 1020-pin FBGA package make it an ideal ASIC prototyping platform. Engineers map RTL designs onto the Stratix II fabric and validate functionality at near-ASIC speeds before committing to fabrication. With 192 DSP blocks and 4.4 Mbit embedded RAM, complex SoCs can be emulated including processor cores, peripherals, and glue logic. The I4 industrial speed grade supports clock rates up to several hundred MHz, sufficient for most pre-silicon validation scenarios.
推荐
High-Speed Digital Signal Processing
The EP2S90F1020I4GA's 192 18x18 hardware multipliers deliver up to ~76 GMACs of DSP throughput, enabling real-time FFTs, FIR filters, and baseband processing. The block RAM supports dual-port operation ideal for sample buffering in radar and software-defined radio pipelines. Combined with 4 PLLs for flexible clock synthesis, this FPGA implements complete digital receivers on a single chip, reducing BOM cost versus discrete DSP + memory architectures in test & measurement equipment.
推荐
Telecom Line Cards
Stratix II FPGAs like the EP2S90F1020I4GA have been widely deployed in telecom line cards for packet processing, SERDES aggregation, and protocol bridging. The 758 user I/O pins support wide parallel backplanes, while external memory interfaces handle DDR/DDR2/QDRII for deep packet buffers. Industrial temperature grade and high logic density make this part suitable for central-office equipment requiring long-life-cycle support and field-proven reliability.
推荐
Test and Measurement Instrumentation
In oscilloscopes, logic analyzers, and protocol analyzers, the EP2S90F1020I4GA provides the parallel processing horsepower to capture and process high-speed signals in real time. The 90,960 LEs support complex trigger state machines, while 758 I/O pins interface directly with high-bandwidth ADCs and DACs. Industrial temperature grade ensures stable operation in lab and field environments, and SRAM-based configuration allows field firmware updates as new protocols emerge.
推荐
Industrial Control and Automation
Programmable logic controllers (PLCs) and motion controllers benefit from the EP2S90F1020I4GA's high I/O count (758 pins) for parallel sensor/actuator interfaces and 192 DSP blocks for real-time servo-loop computation. The industrial -40C to +100C operating range supports deployment in factory floors, outdoor enclosures, and ruggedized mobile equipment. Deterministic SRAM-based configuration enables secure boot for safety-critical industrial applications.
推荐
Military and Aerospace (Legacy Designs)
Established Stratix II designs in defense and aerospace systems continue to use the EP2S90F1020I4GA due to its long product life cycle, industrial temperature range, and mature toolchain support. Its 90,960 LEs handle sensor fusion, video processing, and secure communications payloads. Designers specify this part for legacy programs where re-validation of newer FPGAs would be cost-prohibitive and where the high pin-count FBGA-1020 package integrates seamlessly into existing board layouts.
推荐
推荐产品汇总
工程参考数据： EP2S90F1020I4GA ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EP2S90F1020I4 | EP2S90F1020I3N | EP2S90F1020C5N | EP2S90F1020C4N | EP2S90F1020C3N |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 1020-ball FC-FBGA | 1020-ball FC-FBGA (same) | 1020-ball FC-FBGA (same) | 1020-ball FC-FBGA (same) | 1020-ball FC-FBGA (same) | 1020-ball FC-FBGA (same) |
| Logic Elements (LEs) | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 |
| Speed Grade | I4 | I4 | I3 (slower) | C5 (faster, commercial) | C4 (equivalent, commercial) | C3 (slower, commercial) |
| Temperature Grade | Industrial (-40C to +100C) | Industrial | Industrial | Commercial (0 to 85C) | Commercial (0 to 85C) | Commercial (0 to 85C) |
| Embedded Multipliers (18x18) | 192 | 192 | 192 | 192 | 192 | 192 |
| User I/O Pins | 758 | 758 | 758 | 758 | 758 | 758 |
| RoHS / Lead-Free | Yes (GA suffix) | Yes | Yes (N suffix) | Yes (N suffix) | Yes (N suffix) | Yes (N suffix) |
关键差异点
- Identical silicon and footprint across I/C speed grades （对比 EP2S90F1020C5N (faster commercial speed grade))
- Higher logic density than Stratix II EP2S60 （对比 EP2S60F1020I4 (60K LE on same FBGA-1020 package))
- GA suffix ensures RoHS compliance orderability （对比 EP2S90F1020I4 (bare MPN without GA suffix))
设计说明
The EP2S90F1020I4GA requires four supply rails: VCCINT (1.2 V core), VCCA (analog PLL 1.2 V), VCCIO (1.2 V to 3.3 V per bank), and VCCPD (2.5 V or 3.3 V pre-driver). Stricter ramp-ordering rules apply: VCCINT must precede VCCPD and VCCIO during power-up; consult Stratix II handbook Figure 5-1. Recommended: use a dedicated power management IC with monotonic ramp and minimum 1 ms rise time. Estimated: at full utilization (90,960 LEs switching at 50% toggle rate, 250 MHz) the core current exceeds 3 A; design the VCCINT plane with at least 2 oz copper or 4+ vias per decoupling capacitor.
Estimated: at worst case (1.2 V * 3 A core + I/O bank activity), the EP2S90F1020I4GA can dissipate 5-8 W. The 1020-ball FC-FBGA package has a junction-to-ambient thermal resistance theta_JA of approximately 12-15 C/W with a 4-layer PCB thermal via array under the die. For continuous industrial-temperature operation, an embedded heat spreader or forced airflow is recommended when ambient exceeds 70C. Use the Quartus PowerPlay analyzer to estimate dynamic power per design and derate accordingly.
The 1020-ball FC-FBGA uses a 1.0 mm ball pitch. PCB design must use laser-drilled microvias or stacked-via construction; standard 8-mil vias will not fan-out correctly. Assign at least one full PCB ground plane directly under the BGA for return-current management, and stitch all four power planes with 0.1 uF decoupling capacitors at every VCCIO bank boundary. Place the EPCS configuration memory within 2 inches of the FPGA with controlled-impedance routing for the DATA, DCLK, and nCS signals.
Do not confuse Stratix II (this part, 90 nm) with Stratix II GX (which has transceivers) or Stratix III/IV/V (different pinouts, packages, and voltages). Verify configuration mode strapping (MSEL pins) match the boot source - incorrect MSEL settings cause configuration failure. The 'GA' suffix denotes RoHS orderability; the bare MPN may not be lead-free. Last-time-buy status means order cancellation terms are stricter; commit to volumes early to avoid re-sourcing challenges.
合规信息
RoHS compliance confirmed via GA suffix per Altera/Intel ordering guide. Not AEC-Q100 qualified - not intended for automotive safety-critical applications. For automotive, select Cyclone IV/V or newer automotive-grade FPGAs.