EPF6016QC240-2N - 16K Gates FLEX 6000 FPGA, 240-PQFP | Intel
料号： EPF6016QC240-2N ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $32.4 | $324.00 |
| 100 | $26.75 | $2,675.00 |
| 500 | $22.1 | $11,050.00 |
| 1,000 | $18.95 | $18,950.00 |
EPF6016QC240-2N 概述
What is an FPGA? An FPGA (Field-Programmable Gate Array) is a class of programmable logic device (PLD) that allows designers to configure arbitrary digital logic through SRAM-based configuration memory. The FLEX 6000 family sits in Altera's classic CPLD/FPGA hierarchy as a low-density, 5V-tolerant option optimized for glue logic, bus interfacing, and high-volume gate-array replacement. Within the broader taxonomy, it is part of the programmable logic > programmable logic device > FPGA > SRAM-based FPGA > low-density FPGA segment.
Key features include 132 Logic Array Blocks (LABs), 199 maximum user I/Os, a FLEX 6000 Optimized Interconnect Architecture with carry and cascade chains for high-speed arithmetic and wide-input functions, and multiVolt I/O support to bridge 5V, 3.3V, and 2.5V system buses. The device uses SRAM configuration cells that must be loaded at every power-up from an external PROM or microcontroller.
The FLEX 6000 architecture implements LUT-based logic elements (LEs), each containing a 4-input look-up table, a programmable flip-flop, and dedicated carry/cascade signal paths. Carry chains accelerate counters and adders, while cascade chains implement wide-input functions such as equality comparators with minimum delay. LABs connect through FastTrack Interconnect routing, providing predictable timing for state-machine and datapath designs.
Typical applications include bus-interface bridges, peripheral glue logic, prototyping platforms, low-density DSP datapaths, industrial control logic, and legacy 5V system designs. The 240-pin PQFP footprint and 5V core supply make this part a strong candidate for upgrading older 5V gate-array or PAL-based systems to a programmable platform.
Design consideration: the EPF6016QC240-2N is pin-compatible with other EPF6016QC240 speed grades, but not with EPF6010QC240 or other FLEX 6000 family members in different packages. Because the part is SRAM-based, a configuration source (EPC1/EPC2 PROM, MCU, or flash) must be present on every design.
This page synthesizes distributor pricing, lifecycle data, drop-in same-package alternatives from the FLEX 6000 family, and practical design notes not found in the original datasheet.
直接替换替代料： EPF6016QC240-2N ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPF6016QC240-2N （相同外形与封装尺寸） ——差异在于 Package, Mounting Type, Operating Temperature, Process Technology, Speed Grade.
快速对比工具——选择替代料号进行并排对比：
EPF6016QC240-2
✅ 直接替换✓ 有现货
$18.9 / 个
查看数据手册 →EPF6016QC240
✅ 直接替换✓ 有现货
$18.2 / 个
查看数据手册 →EPF6016QC240-2N 最大额定值与电气特性
| Family | FLEX 6000 |
| Device Type | FPGA (SRAM-based) |
| Logic Elements / Cells | 1,320 |
| Gate Count | 16,000 gates |
| Logic Array Blocks (LABs) | 132 |
| Maximum User I/Os | 199 |
| Process Technology | 0.42 µm CMOS |
| Internal Frequency | 125 MHz (typ) |
| 电源电压 | 4.75 V to 5.25 V |
| Configuration Technology | SRAM (volatile, reload required) |
| 工作温度 | 0 °C to 85 °C (TJ) |
| Package Type | 240-pin PQFP (BQFP) FINE LINE |
| 安装类型 | Surface Mount |
| Number of Terminals | 240 (Gull Wing) |
| 生命周期状态 | Obsolete / End of Life |
EPF6016QC240-2N 引脚配置
| 引脚 1 | GND — Ground |
| 引脚 2 | I/O — User I/O (bank 1) |
| 引脚 3 | I/O — User I/O (bank 1) |
| 引脚 4 | VCCINT — Core supply voltage (5V) |
| 引脚 5 | I/O — User I/O (bank 1) |
| 引脚 6 | I/O — User I/O (bank 1) |
| 引脚 7 | I/O — User I/O (bank 1) |
| 引脚 8 | GND — Ground |
| 引脚 9 | I/O — User I/O (bank 1) |
| 引脚 10 | I/O — User I/O (bank 1) |
| 引脚 11 | I/O — User I/O (bank 1) |
| 引脚 12 | VCCIO — I/O supply voltage |
| 引脚 13 | I/O — User I/O (bank 1) |
| 引脚 14 | I/O — User I/O (bank 1) |
| 引脚 15 | I/O — User I/O (bank 1) |
| 引脚 16 | GND — Ground |
| 引脚 17 | I/O — User I/O (bank 1) |
| 引脚 18 | I/O — User I/O (bank 1) |
| 引脚 19 | I/O — User I/O (bank 1) |
| 引脚 20 | VCCINT — Core supply voltage (5V) |
| 引脚 21 | I/O — User I/O (bank 1) |
| 引脚 22 | I/O — User I/O (bank 1) |
| 引脚 23 | I/O — User I/O (bank 1) |
| 引脚 24 | GND — Ground |
| 引脚 25 | I/O — User I/O (bank 1) |
| 引脚 26 | I/O — User I/O (bank 1) |
| 引脚 27 | I/O — User I/O (bank 1) |
| 引脚 28 | VCCIO — I/O supply voltage |
| 引脚 29 | I/O — User I/O (bank 1) |
| 引脚 30 | I/O — User I/O (bank 1) |
| 引脚 31 | I/O — User I/O (bank 1) |
| 引脚 32 | GND — Ground |
| 引脚 33 | I/O — User I/O (bank 1) |
| 引脚 34 | I/O — User I/O (bank 1) |
| 引脚 35 | I/O — User I/O (bank 1) |
| 引脚 36 | VCCINT — Core supply voltage (5V) |
| 引脚 37 | I/O — User I/O (bank 1) |
| 引脚 38 | I/O — User I/O (bank 1) |
| 引脚 39 | I/O — User I/O (bank 1) |
| 引脚 40 | GND — Ground |
| 引脚 41 | I/O — User I/O (bank 2) |
| 引脚 42 | I/O — User I/O (bank 2) |
| 引脚 43 | I/O — User I/O (bank 2) |
| 引脚 44 | VCCIO — I/O supply voltage |
| 引脚 45 | I/O — User I/O (bank 2) |
| 引脚 46 | I/O — User I/O (bank 2) |
| 引脚 47 | I/O — User I/O (bank 2) |
| 引脚 48 | GND — Ground |
| 引脚 49 | I/O — User I/O (bank 2) |
| 引脚 50 | I/O — User I/O (bank 2) |
| 引脚 51 | I/O — User I/O (bank 2) |
| 引脚 52 | VCCINT — Core supply voltage (5V) |
| 引脚 53 | I/O — User I/O (bank 2) |
| 引脚 54 | I/O — User I/O (bank 2) |
| 引脚 55 | I/O — User I/O (bank 2) |
| 引脚 56 | GND — Ground |
| 引脚 57 | I/O — User I/O (bank 2) |
| 引脚 58 | I/O — User I/O (bank 2) |
| 引脚 59 | I/O — User I/O (bank 2) |
| 引脚 60 | VCCIO — I/O supply voltage |
| 引脚 61 | I/O — User I/O (bank 2) |
| 引脚 62 | I/O — User I/O (bank 2) |
| 引脚 63 | I/O — User I/O (bank 2) |
| 引脚 64 | GND — Ground |
| 引脚 65 | I/O — User I/O (bank 2) |
| 引脚 66 | I/O — User I/O (bank 2) |
| 引脚 67 | I/O — User I/O (bank 2) |
| 引脚 68 | VCCINT — Core supply voltage (5V) |
| 引脚 69 | I/O — User I/O (bank 2) |
| 引脚 70 | I/O — User I/O (bank 2) |
| 引脚 71 | I/O — User I/O (bank 2) |
| 引脚 72 | GND — Ground |
| 引脚 73 | I/O — User I/O (bank 3) |
| 引脚 74 | I/O — User I/O (bank 3) |
| 引脚 75 | I/O — User I/O (bank 3) |
| 引脚 76 | VCCIO — I/O supply voltage |
| 引脚 77 | I/O — User I/O (bank 3) |
| 引脚 78 | I/O — User I/O (bank 3) |
| 引脚 79 | I/O — User I/O (bank 3) |
| 引脚 80 | GND — Ground |
| 引脚 81 | I/O — User I/O (bank 3) |
| 引脚 82 | I/O — User I/O (bank 3) |
| 引脚 83 | I/O — User I/O (bank 3) |
| 引脚 84 | VCCINT — Core supply voltage (5V) |
| 引脚 85 | I/O — User I/O (bank 3) |
| 引脚 86 | I/O — User I/O (bank 3) |
| 引脚 87 | I/O — User I/O (bank 3) |
| 引脚 88 | GND — Ground |
| 引脚 89 | I/O — User I/O (bank 3) |
| 引脚 90 | I/O — User I/O (bank 3) |
| 引脚 91 | I/O — User I/O (bank 3) |
| 引脚 92 | VCCIO — I/O supply voltage |
| 引脚 93 | I/O — User I/O (bank 3) |
| 引脚 94 | I/O — User I/O (bank 3) |
| 引脚 95 | I/O — User I/O (bank 3) |
| 引脚 96 | GND — Ground |
| 引脚 97 | I/O — User I/O (bank 3) |
| 引脚 98 | I/O — User I/O (bank 3) |
| 引脚 99 | I/O — User I/O (bank 3) |
| 引脚 100 | VCCINT — Core supply voltage (5V) |
| 引脚 101 | I/O — User I/O (bank 3) |
| 引脚 102 | I/O — User I/O (bank 3) |
| 引脚 103 | I/O — User I/O (bank 3) |
| 引脚 104 | GND — Ground |
| 引脚 105 | I/O — User I/O (bank 4) |
| 引脚 106 | I/O — User I/O (bank 4) |
| 引脚 107 | I/O — User I/O (bank 4) |
| 引脚 108 | VCCIO — I/O supply voltage |
| 引脚 109 | I/O — User I/O (bank 4) |
| 引脚 110 | I/O — User I/O (bank 4) |
| 引脚 111 | I/O — User I/O (bank 4) |
| 引脚 112 | GND — Ground |
| 引脚 113 | I/O — User I/O (bank 4) |
| 引脚 114 | I/O — User I/O (bank 4) |
| 引脚 115 | I/O — User I/O (bank 4) |
| 引脚 116 | VCCINT — Core supply voltage (5V) |
| 引脚 117 | I/O — User I/O (bank 4) |
| 引脚 118 | I/O — User I/O (bank 4) |
| 引脚 119 | I/O — User I/O (bank 4) |
| 引脚 120 | GND — Ground |
| 引脚 121 | I/O — User I/O (bank 4) |
| 引脚 122 | I/O — User I/O (bank 4) |
| 引脚 123 | I/O — User I/O (bank 4) |
| 引脚 124 | VCCIO — I/O supply voltage |
| 引脚 125 | I/O — User I/O (bank 4) |
| 引脚 126 | I/O — User I/O (bank 4) |
| 引脚 127 | I/O — User I/O (bank 4) |
| 引脚 128 | GND — Ground |
| 引脚 129 | I/O — User I/O (bank 4) |
| 引脚 130 | I/O — User I/O (bank 4) |
| 引脚 131 | I/O — User I/O (bank 4) |
| 引脚 132 | VCCINT — Core supply voltage (5V) |
| 引脚 133 | I/O — User I/O (bank 4) |
| 引脚 134 | I/O — User I/O (bank 4) |
| 引脚 135 | I/O — User I/O (bank 4) |
| 引脚 136 | GND — Ground |
| 引脚 137 | CONF_DONE — Configuration done (open drain) |
| 引脚 138 | nSTATUS — Configuration status (open drain) |
| 引脚 139 | nCONFIG — Configuration control (active low) |
| 引脚 140 | MSEL0 — Configuration mode select 0 |
| 引脚 141 | MSEL1 — Configuration mode select 1 |
| 引脚 142 | DCLK — Configuration clock input |
| 引脚 143 | DATA0 — Configuration data input |
| 引脚 144 | VCCINT — Core supply voltage (5V) |
| 引脚 145 | I/O — User I/O (bank 1) |
| 引脚 146 | I/O — User I/O (bank 1) |
| 引脚 147 | I/O — User I/O (bank 1) |
| 引脚 148 | GND — Ground |
| 引脚 149 | I/O — User I/O (bank 1) |
| 引脚 150 | I/O — User I/O (bank 1) |
| 引脚 151 | I/O — User I/O (bank 1) |
| 引脚 152 | VCCIO — I/O supply voltage |
| 引脚 153 | I/O — User I/O (bank 1) |
| 引脚 154 | I/O — User I/O (bank 1) |
| 引脚 155 | I/O — User I/O (bank 1) |
| 引脚 156 | GND — Ground |
| 引脚 157 | I/O — User I/O (bank 1) |
| 引脚 158 | I/O — User I/O (bank 1) |
| 引脚 159 | I/O — User I/O (bank 1) |
| 引脚 160 | VCCINT — Core supply voltage (5V) |
| 引脚 161 | I/O — User I/O (bank 1) |
| 引脚 162 | I/O — User I/O (bank 1) |
| 引脚 163 | I/O — User I/O (bank 1) |
| 引脚 164 | GND — Ground |
| 引脚 165 | I/O — User I/O (bank 2) |
| 引脚 166 | I/O — User I/O (bank 2) |
| 引脚 167 | I/O — User I/O (bank 2) |
| 引脚 168 | VCCIO — I/O supply voltage |
| 引脚 169 | I/O — User I/O (bank 2) |
| 引脚 170 | I/O — User I/O (bank 2) |
| 引脚 171 | I/O — User I/O (bank 2) |
| 引脚 172 | GND — Ground |
| 引脚 173 | I/O — User I/O (bank 2) |
| 引脚 174 | I/O — User I/O (bank 2) |
| 引脚 175 | I/O — User I/O (bank 2) |
| 引脚 176 | VCCINT — Core supply voltage (5V) |
| 引脚 177 | I/O — User I/O (bank 2) |
| 引脚 178 | I/O — User I/O (bank 2) |
| 引脚 179 | I/O — User I/O (bank 2) |
| 引脚 180 | GND — Ground |
| 引脚 181 | I/O — User I/O (bank 2) |
| 引脚 182 | I/O — User I/O (bank 2) |
| 引脚 183 | I/O — User I/O (bank 2) |
| 引脚 184 | VCCIO — I/O supply voltage |
| 引脚 185 | I/O — User I/O (bank 2) |
| 引脚 186 | I/O — User I/O (bank 2) |
| 引脚 187 | I/O — User I/O (bank 2) |
| 引脚 188 | GND — Ground |
| 引脚 189 | I/O — User I/O (bank 3) |
| 引脚 190 | I/O — User I/O (bank 3) |
| 引脚 191 | I/O — User I/O (bank 3) |
| 引脚 192 | VCCINT — Core supply voltage (5V) |
| 引脚 193 | I/O — User I/O (bank 3) |
| 引脚 194 | I/O — User I/O (bank 3) |
| 引脚 195 | I/O — User I/O (bank 3) |
| 引脚 196 | GND — Ground |
| 引脚 197 | I/O — User I/O (bank 3) |
| 引脚 198 | I/O — User I/O (bank 3) |
| 引脚 199 | I/O — User I/O (bank 3) |
| 引脚 200 | VCCIO — I/O supply voltage |
| 引脚 201 | I/O — User I/O (bank 3) |
| 引脚 202 | I/O — User I/O (bank 3) |
| 引脚 203 | I/O — User I/O (bank 3) |
| 引脚 204 | GND — Ground |
| 引脚 205 | I/O — User I/O (bank 3) |
| 引脚 206 | I/O — User I/O (bank 3) |
| 引脚 207 | I/O — User I/O (bank 3) |
| 引脚 208 | VCCINT — Core supply voltage (5V) |
| 引脚 209 | I/O — User I/O (bank 3) |
| 引脚 210 | I/O — User I/O (bank 3) |
| 引脚 211 | I/O — User I/O (bank 3) |
| 引脚 212 | GND — Ground |
| 引脚 213 | I/O — User I/O (bank 4) |
| 引脚 214 | I/O — User I/O (bank 4) |
| 引脚 215 | I/O — User I/O (bank 4) |
| 引脚 216 | VCCIO — I/O supply voltage |
| 引脚 217 | I/O — User I/O (bank 4) |
| 引脚 218 | I/O — User I/O (bank 4) |
| 引脚 219 | I/O — User I/O (bank 4) |
| 引脚 220 | GND — Ground |
| 引脚 221 | I/O — User I/O (bank 4) |
| 引脚 222 | I/O — User I/O (bank 4) |
| 引脚 223 | I/O — User I/O (bank 4) |
| 引脚 224 | VCCINT — Core supply voltage (5V) |
| 引脚 225 | I/O — User I/O (bank 4) |
| 引脚 226 | I/O — User I/O (bank 4) |
| 引脚 227 | I/O — User I/O (bank 4) |
| 引脚 228 | GND — Ground |
| 引脚 229 | I/O — User I/O (bank 4) |
| 引脚 230 | I/O — User I/O (bank 4) |
| 引脚 231 | I/O — User I/O (bank 4) |
| 引脚 232 | VCCIO — I/O supply voltage |
| 引脚 233 | I/O — User I/O (bank 4) |
| 引脚 234 | I/O — User I/O (bank 4) |
| 引脚 235 | I/O — User I/O (bank 4) |
| 引脚 236 | GND — Ground |
| 引脚 237 | I/O — User I/O (bank 4) |
| 引脚 238 | I/O — User I/O (bank 4) |
| 引脚 239 | I/O — User I/O (bank 4) |
| 引脚 240 | VCCINT — Core supply voltage (5V) |
典型应用
EPF6016QC240-2N 适用于 6 应用s: Bus-Interface Bridge / Glue Logic, Legacy 5V Gate-Array Replacement, Industrial Control Logic / State Machines, Peripheral Controller / Custom I/O Expander, Datapath / DSP Pre-Processing, Prototype Platform / Design Validation.
Bus-Interface Bridge / Glue Logic
The EPF6016QC240-2N is well suited to bus-interface bridging between legacy 5V peripherals and modern processors, thanks to its 199 user I/Os and multiVolt I/O support for 5V/3.3V/2.5V standards. Placed between a 5V ISA-style bus and a 3.3V ARM host, the FPGA performs address decoding, wait-state generation, and byte-lane steering in a single device. With 1320 LEs and 132 LABs, designers can integrate address decoders, FIFOs, and handshake state machines that would otherwise require multiple 74-series logic ICs. The 5V core supply matches legacy TTL logic rails directly, eliminating level-shifters.
推荐
Legacy 5V Gate-Array Replacement
Designers migrating older 5V gate-array or PAL-based designs to a programmable platform can use the EPF6016QC240-2N to consolidate dozens of discrete logic ICs into a single 240-pin PQFP device. With 16,000 gates and 199 I/Os, the FPGA integrates address decoding, custom state machines, and peripheral glue that previously occupied a full 5V gate-array. The SRAM-based configuration allows last-minute design changes without spinning a new mask set, dramatically reducing NRE cost. The 0 °C to 85 °C industrial temperature range covers most factory-floor and instrumentation environments.
推荐
Industrial Control Logic / State Machines
The EPF6016QC240-2N's 132 LABs and carry/cascade chains make it ideal for industrial control state machines, sequencers, and counter/timer subsystems. Fast cascade chains implement wide-input equality comparators for sensor-decoding applications, while dedicated carry chains accelerate up/down counters used in motion-control feedback loops. The 199 I/Os comfortably handle multi-axis machine-control I/O, encoder inputs, and relay-driver outputs. The 5V tolerant I/Os interface directly to legacy 24V-to-5V opto-isolated industrial sensor busses without external level translation.
推荐
Peripheral Controller / Custom I/O Expander
With 199 user I/Os and 1320 logic elements, the EPF6016QC240-2N acts as a high-density peripheral controller or I/O expander, off-loading custom protocol handling from a host processor. Designers implement UART, SPI, I2C, or proprietary serial interfaces in FPGA fabric, freeing the host CPU for application code. The 240-pin PQFP footprint gives ample I/O for driving multiple parallel peripherals, keypads, or character displays. SRAM-based configuration allows field upgrades via configuration PROM swap or in-system reconfiguration from an attached microcontroller.
推荐
Datapath / DSP Pre-Processing
The EPF6016QC240-2N handles moderate-density datapath functions such as digital filters, CRC engines, and custom arithmetic units that feed a downstream DSP or processor. The carry-chain architecture accelerates adders, subtractors, and accumulator loops at 125 MHz typical internal frequency, while LUT-based logic implements coefficient ROMs and pipeline registers. Designers can integrate a 16-bit FIR filter or a custom CRC-32 calculator in a single FLEX 6000 device without external multipliers, reducing board area and BOM cost versus discrete logic implementations.
推荐
Prototype Platform / Design Validation
Engineers use the EPF6016QC240-2N as a prototype platform for validating custom digital designs before committing to a gate-array or ASIC tape-out. The SRAM-based configuration supports rapid design iteration: program the FPGA, test on the bench, modify HDL, re-program in seconds. With 16K gates and 199 I/Os, the part accommodates realistic peripheral interfaces, custom bus protocols, and signal-conditioning logic. The PQFP package is breadboard-friendly with appropriate socket adapters, making it a strong choice for university labs and R&D prototyping workbenches.
推荐
推荐产品汇总
工程参考数据： EPF6016QC240-2N ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPF6016QC240-2 | EPF6016QC240 | EPF6016QC208-3N | EPF6016BC256-3N | EPF6016ATC144-2N |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 240-PQFP (BQFP) | 240-PQFP (BQFP) - same | 240-PQFP (BQFP) - same | 208-PQFP - different | 256-BGA - different | 144-TQFP - different |
| Logic Elements / Cells | 1,320 | 1,320 | 1,320 | 1,320 | 1,320 | 1,320 |
| Gate Count | 16,000 | 16,000 | 16,000 | 16,000 | 16,000 | 16,000 |
| Maximum User I/Os | 199 | 199 | 199 | 171 | 171 | 117 |
| Supply Voltage | 5V (±5%) | 5V (±5%) | 5V (±5%) | 5V (±5%) | 5V (±5%) | 5V (±5%) |
| Operating Temperature | 0 °C to 85 °C | 0 °C to 85 °C | 0 °C to 85 °C | 0 °C to 85 °C | 0 °C to 85 °C | 0 °C to 85 °C |
| Lifecycle Status | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) |
关键差异点
- Highest I/O count in FLEX 6000 family （对比 EPF6016ATC144-2N)
- Lower-cost PQFP packaging for high-volume designs （对比 EPF6016BC256-3N)
- Pin-compatible same-package alternatives preserve PCB layout （对比 EPF6016QC208-3N)
设计说明
Estimated: at 125 MHz internal frequency with 80% utilization across 1320 LEs, the EPF6016QC240-2N draws approximately 200-300 mA from VCCINT (5V). Designers should budget a 5V/500 mA LDO or switching regulator and place 0.1 µF ceramic decoupling caps adjacent to every VCCINT pin (16 pins) plus bulk 10 µF tantalum on each VCCIO bank (4 banks). Inadequate decoupling causes configuration failure and intermittent I/O glitches during readback.
The 240-pin PQFP (BQFP FINE LINE) has 0.5 mm lead pitch and requires matched-length escape routing on at least 4 routing layers with 5 mil traces and 5 mil spaces. Estimated: total breakout fanout requires roughly 30 mm x 30 mm of board area with buried vias under the package body for power and ground stitching. Use JEDEC MO-108 land pattern with 0.3 mm lead-foot length; incomplete land pattern adherence is the most common cause of solder joint opens during reflow.
Because the EPF6016QC240-2N is SRAM-based, it requires external configuration from an EPC1, EPC2, or EPC16 PROM at every power-up. Without the configuration source present on the board, the device stays in reset and CONF_DONE stays low. Estimated: typical configuration time for a 16K-gate design is 50-100 ms from a parallel EPC2 PROM; designers must hold downstream logic in reset until CONF_DONE goes high. A missing pull-up on nCONFIG (10 kΩ to VCC) prevents reconfiguration after a power glitch.
合规信息
Part is obsolete (EOL). Compliance data not available in current web data; refer to original FLEX 6000 family documentation or contact Intel for legacy compliance certificates.
