EPM5192ALI84-15 - 192-Macrocell OTP PLD, 84-PQCC | Altera
料号： EPM5192ALI84-15 ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.95 | $9,950.00 |
EPM5192ALI84-15 概述
A Complex PLD (CPLD predecessor) is a non-volatile programmable logic device that combines multiple AND/OR macrocell arrays on a single die. The EPM5192 belongs to the MAX 5000 family - Altera's high-density, high-speed, UV-erasable/OTP CMOS PLD series positioned between classic PAL/GAL devices and modern MAX II CPLDs. Within the broader programmable logic taxonomy, this device sits in the hierarchy: macrocell-based PLD -> MAX 5000 family -> UV-erasable/OTP Complex PLD -> programmable logic -> semiconductor IC.
Key features of the EPM5192ALI84-15 include 192 logic macrocells, 7 dedicated input pins, 64 bidirectional I/O pins supporting up to 72 total input channels, propagation delay tPD of 25 ns (-15 speed grade), and CMOS non-volatile OTP programming via on-chip EPROM cells. The device is offered in industrial grade (-40C to +85C). The PQCC J-Lead package (JESD-30 S-PQCC-J84) is socket-compatible with standard PLCC-84 sockets, easing field replacement and programming-socket tooling.
Typical applications include legacy bus-interface glue logic in industrial controllers, address decoding and wait-state generation in 8/16/20 MHz microprocessor systems, replacement of discrete 7400-series TTL glue, and high-pin-count state-machine integration in through-hole assembly lines where modern BGA/QFP CPLDs are not pin-compatible. The OTP architecture is suitable for production-volume designs where design changes are infrequent.
Design consideration: confirm availability of compatible 84-pin PLCC programming sockets before PCB layout commit; modern CPLDs in fine-pitch QFP/BGA do NOT drop in. For new designs, consider MAX II or MAX V CPLDs as a migration path only if PCB layout can be changed.
This page synthesizes EPM5192ALI84-15 distributor availability, package/die siblings, and field-replacement guidance not consolidated on the manufacturer datasheet.
直接替换替代料： EPM5192ALI84-15 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPM5192ALI84-15 （相同外形与封装尺寸） ——差异在于 Mounting Type, Device Type, Process Technology, Propagation Delay (tPD), Package Type.
快速对比工具——选择替代料号进行并排对比：
EPM5192ALI84-20
✅ 直接替换✓ 有现货
$9.9 / 个
查看数据手册 →EPM5192ALC84-15
✅ 直接替换✓ 有现货
$13.2 / 个
查看数据手册 →EPM5192ALC84-20
✅ 直接替换✓ 有现货
$19.4 / 个
查看数据手册 →EPM5192AJI84-15
✅ 直接替换✓ 有现货
$27.8 / 个
查看数据手册 →EPM5192AJI84-20
✅ 直接替换✓ 有现货
$10.95 / 个
查看数据手册 →EPM5192ALI84-15 最大额定值与电气特性
| Device Family | MAX 5000 |
| Product Type | UV-Erasable / OTP Complex PLD |
| Logic Macrocells | 192 |
| Dedicated Inputs | 7 |
| Bidirectional I/O Pins | 64 |
| Maximum Total Inputs | 72 |
| Propagation Delay (tPD) | 25 ns (-15 speed grade) |
| Process Technology | CMOS, non-volatile EPROM/OTP |
| Programmability | One-Time Programmable (windowless) |
| 封装 | 84-pin PQCC (PLCC, J-Lead) |
| JEDEC JESD-30 Code | S-PQCC-J84 |
| Terminal Form | J Bend (J-Lead) |
| Operating Temperature Grade | Industrial |
| 安装类型 | Surface Mount (PLCC socket compatible) |
EPM5192ALI84-15 引脚配置
| 引脚 1 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 2 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 3 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 4 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 5 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 6 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 7 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 8 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 9 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 10 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 11 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 12 | GND — Ground |
| 引脚 13 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 14 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 15 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 16 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 17 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 18 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 19 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 20 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 21 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 22 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 23 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 24 | VCC — Supply voltage |
| 引脚 25 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 26 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 27 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 28 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 29 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 30 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 31 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 32 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 33 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 34 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 35 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 36 | GND — Ground |
| 引脚 37 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 38 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 39 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 40 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 41 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 42 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 43 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 44 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 45 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 46 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 47 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 48 | VCC — Supply voltage |
| 引脚 49 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 50 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 51 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 52 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 53 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 54 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 55 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 56 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 57 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 58 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 59 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 60 | GND — Ground |
| 引脚 61 | INPUT/GCLK — Dedicated input or global clock |
| 引脚 62 | INPUT/OE — Dedicated input or output enable |
| 引脚 63 | INPUT — Dedicated input |
| 引脚 64 | INPUT — Dedicated input |
| 引脚 65 | INPUT — Dedicated input |
| 引脚 66 | INPUT — Dedicated input |
| 引脚 67 | INPUT — Dedicated input |
| 引脚 68 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 69 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 70 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 71 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 72 | VCC — Supply voltage |
| 引脚 73 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 74 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 75 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 76 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 77 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 78 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 79 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 80 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 81 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 82 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 83 | I/O — Bidirectional I/O pin (macrocell) |
| 引脚 84 | I/O — Bidirectional I/O pin (macrocell) |
典型应用
EPM5192ALI84-15 适用于 6 应用s: Legacy Microprocessor Glue Logic, Industrial Controller Address Decoding, State Machine Integration, VMEbus / Multibus Interface Logic, 7400-Series TTL Replacement, Legacy Equipment Repair and Sustaining.
Legacy Microprocessor Glue Logic
The EPM5192ALI84-15's 192 macrocells and 25 ns propagation delay suit legacy 8/16/20 MHz microprocessor bus-interface glue logic. In systems using 80C186, 68k, or Z80 processors, it consolidates address decoding, wait-state generation, chip-select logic, and interrupt prioritization into a single 84-PLCC, replacing 5-10 discrete 74LS/74F PAL/GAL devices. The windowless OTP architecture is ideal for production units where the design is finalized - prototype builds can use the windowed LC84 variant for UV-erase iterations. The 72-input capacity accommodates the full 20-bit address bus plus control signals. Migration to modern MAX II/MAX V CPLDs is recommended for new designs requiring Flash reprogrammability.
推荐
Industrial Controller Address Decoding
In industrial PLC and process-control backplanes, the EPM5192ALI84-15 provides reliable address decoding for I/O expansion modules and memory-mapped peripherals. The 192-macrocell capacity supports up to 192 independent chip-select or enable signals, while the 25 ns tPD maintains timing margin with ISA bus cycles (~120 ns minimum) and VMEbus. The industrial temperature grade (-40C to 85C) tolerates factory-floor environments. The 84-pin PQCC package is socket-compatible for field replacement in legacy installations - critical for industrial systems with 20+ year service lives where the original Altera PLDs must be replaced as they reach end-of-life. No cross-brand equivalent shares the 84-PLCC footprint.
推荐
State Machine Integration
The EPM5192ALI84-15 is well suited to large state-machine integration in control panels, where multiple discrete TTL state machines need to be consolidated into one device. Each of the 192 macrocells can implement a registered state bit with combinatorial next-state logic, supporting FSMs with 50+ states and complex transition graphs. The OTP programming is appropriate for production units once the FSM is validated, while the 25 ns tPD enables state transitions at up to ~20 MHz. The 64 I/O pins interface directly to 5V logic. Designers should note that the OTP architecture prevents in-system reprogramming - design changes require a new programmed part, so prototype with the windowed LC84 variant before committing to OTP.
推荐
VMEbus / Multibus Interface Logic
In VMEbus and Multibus backplane systems, the EPM5192ALI84-15 implements bus arbitration, interrupt acknowledge, and address-modifier decoding with timing that meets the 25 ns bus-signal requirements. The 192 macrocells support multiple parallel arbitration schemes, while the 7 dedicated inputs accept bus-grant and request signals. The PQCC-84 package and CMOS EPROM technology have proven reliability in long-lifecycle aerospace, defense, and industrial VME installations. For new VME designs, consider the MAX II EPM240 or MAX V EPM570, but for legacy VME backplane repair, the EPM5192ALI84-15 remains the original-fit part. The industrial temperature grade tolerates chassis-internal temperatures up to 85C.
推荐
7400-Series TTL Replacement
The EPM5192ALI84-15 is a one-for-many replacement for 7400-series TTL glue logic in legacy through-hole designs. A single EPM5192ALI84-15 typically replaces 10-20 discrete 74LS/74F/74AS chips (decoders, multiplexers, latches, parity generators, comparators), reducing board area, power consumption, and BOM cost. The OTP programming is well-suited to designs where the glue logic is finalized and replicated across many production units. The 84-PLCC footprint fits on legacy boards designed around DIP-20/24 sockets with adapter boards. For new TTL-replacement designs, evaluate the EPM240 (MAX II) which provides similar density in a smaller TQFP-100 package with Flash reprogrammability.
推荐
Legacy Equipment Repair and Sustaining
The primary modern use of the EPM5192ALI84-15 is sustaining engineering for legacy equipment with installed bases of 20+ years. Aerospace test equipment, military radios, industrial process controllers, and scientific instruments originally designed in the 1990s use this PLD as glue logic. When a unit fails in the field, a replacement programmed EPM5192ALI84-15 can be socketed in directly - the PQCC-84 form factor uses standard test-burn-in sockets available from 3M, Yamaichi, and Wells-CTI. Independent distributors (Jotrin, Microchip USA, FPGAkey) maintain limited stock. For new equipment, MAX II/MAX V CPLDs are the recommended replacement path, but the EPM5192ALI84-15 remains irreplaceable for legacy repair.
推荐
推荐产品汇总
工程参考数据： EPM5192ALI84-15 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPM5192ALI84-20 | EPM5192ALC84-15 | EPM5192ALC84-20 | EPM5192AJI84-15 | EPM5192AJI84-20 |
|---|---|---|---|---|---|---|
| Package | 84-pin PQCC (PLCC, J-Lead) | 84-pin PQCC (PLCC, J-Lead) - same | 84-pin PQCC (PLCC, J-Lead) - same | 84-pin PQCC (PLCC, J-Lead) - same | 84-pin PQCC (PLCC, J-Lead) - same | 84-pin PQCC (PLCC, J-Lead) - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Logic Macrocells | 192 | 192 | 192 | 192 | 192 | 192 |
| Propagation Delay (tPD) | 25 ns (-15 speed grade) | 20 ns (-20 grade, faster) | 25 ns (-15 grade) | 20 ns (-20 grade) | 25 ns (-15 grade) | 20 ns (-20 grade) |
| Temperature Grade | Industrial (-40C to 85C) | Industrial | Commercial (0C to 70C) | Commercial (0C to 70C) | Military (-55C to 125C) | Military (-55C to 125C) |
| Programmability | OTP (windowless) | OTP (windowless) | UV-erasable (windowed) | UV-erasable (windowed) | OTP (windowless) | OTP (windowless) |
| Bidirectional I/O Pins | 64 | 64 | 64 | 64 | 64 | 64 |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Pin Count | 84 | 84 | 84 | 84 | 84 | 84 |
关键差异点
- Windowless OTP architecture suited for production volume （对比 EPM5192ALC84-15)
- Industrial temperature grade for harsh environments （对比 EPM5192ALC84-15)
- Faster -15 grade with full industrial qualification （对比 EPM5192ALI84-20)
设计说明
The EPM5192ALI84-15 is windowless OTP - once programmed it CANNOT be erased or reprogrammed. Always validate the JEDEC fuse map with a windowed EPM5192ALC84-15 (UV-erasable) prototype before committing to OTP volume production. Programming failures on OTP parts are permanent and the device is destroyed. Estimated prototype-to-production workflow: program LC84, UV-erase, iterate; once design is frozen, program LI84 for production.
The 84-pin PQCC (PLCC) J-Lead package uses standard 84-pin PLCC sockets (1.27 mm pitch). Recommended sockets include 3M 8400-series, Yamaichi IC149-084-£ series, and Wells-CTI 84-pin PLCC sockets. For field-replaceable designs, use a socketed footprint rather than direct PCB soldering to enable EOL replacement. Direct soldering of PLCC J-leads to PCB is feasible but complicates rework. The PLCC package is NOT pin-compatible with QFP/BGA modern CPLDs - any migration to MAX II/MAX V requires a complete PCB redesign.
The EPM5192ALI84-15 in industrial temperature grade operates from -40C to +85C ambient, with CMOS EPROM technology typical quiescent current of approximately 100-200 mA at 5V VCC depending on output switching activity. Estimated: at full 64 I/O switching at 5 MHz, dynamic current adds 30-50 mA. Provide at least 4 PCB VCC/GND decoupling capacitors (0.1 uF ceramic) placed within 5 mm of each package VCC pin to suppress switching noise on the EPROM programming lines and output banks. The PLCC package has moderate theta_JA (~40-50 C/W in still air); ensure adequate airflow in enclosed chassis.
合规信息
Compliance information not available in provided web data. The EPM5192ALI84-15 is a legacy Altera (now Intel) CMOS EPROM device from the 1990s; RoHS compliance for the LI84 suffix (industrial, OTP) was not confirmed in retrieved sources. Pre-2005 Altera products are commonly non-RoHS unless explicitly marked Pb-Free.
