EPM5192AJI84-15 - 192-Macrocell UV PLD, 15ns | Altera
料号： EPM5192AJI84-15 ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $48.5 | $48.50 |
| 10 | $42 | $420.00 |
| 100 | $36.5 | $3,650.00 |
| 500 | $31.2 | $15,600.00 |
| 1,000 | $27.8 | $27,800.00 |
EPM5192AJI84-15 概述
A Programmable Logic Device (PLD) is a class of digital integrated circuit whose logic function and interconnect are defined by on-chip programmable fuses, anti-fuses, or floating-gate memory cells rather than at the mask level. In the broader system hierarchy, PLDs sit between discrete TTL/CMOS glue logic and mask-programmed gate arrays: they offer higher integration than 74-series logic, lower NRE cost than full ASICs, and faster iteration cycles than mask-programmed gate arrays. The MAX 5000 family's UV-erasable windowed package made it a 1990s workhorse for prototyping and low-volume production.
Key features of the EPM5192AJI84-15 include 192 macrocells organized as 16 Logic Array Blocks (LABs) of 16 macrocells each, 84 bi-directional I/O pins, a 15 ns pin-to-pin propagation delay (tPD) enabling 50 MHz+ state-machine operation, and an internal 5 V CMOS EPROM process technology. The 'J' suffix indicates the JLCC (J-Leaded Ceramic Chip Carrier) windowed package, and 'I' designates the industrial operating temperature range of -40 °C to +85 °C.
The architecture combines a global programmable interconnect array with LAB-local routing, allowing efficient implementation of wide combinational and registered logic functions such as address decoders, bus arbitrators, state machines, and peripheral controllers. The 84-pin JLCC package with quartz window supports UV erasure for re-programming during development, after which the device is typically windowed-over or replaced with the OTP 'C' (plastic) variant for production.
Typical applications include legacy 5 V system glue logic, industrial control and instrumentation, military and aerospace prototyping (where MIL-STD-883 variants exist), telecom backplane controllers, and field-replaceable logic modules. The wide 5 V supply tolerance and high I/O count make it well-suited to bus-interface and address-decoding tasks in 8-/16-bit microprocessor systems.
When designing with this part, verify that downstream tooling (MAX+PLUS II baseline or legacy Altera designers) is available, since modern Quartus Prime does not support the MAX 5000 family. Decoupling per MAX 5000 reference designs and respect for the UV-erase programming sequence are essential for first-time-programming success.
This page synthesizes distributor pricing, pin-compatible MAX 5000 family alternatives, and practical migration notes not consolidated in any single legacy datasheet, helping engineers source and qualify obsolete Altera EPLDs.
直接替换替代料： EPM5192AJI84-15 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPM5192AJI84-15 （相同外形与封装尺寸） ——差异在于 Package, Mounting Type, Device Type, Process Technology, Propagation Delay (tPD).
快速对比工具——选择替代料号进行并排对比：
EPM5192AJC84-15
✅ 直接替换✓ 有现货
$18.95 / 个
查看数据手册 →EPM5192AGC84-15
✅ 直接替换✓ 有现货
$42 / 个
查看数据手册 →EPM5192AJC84-20
✅ 直接替换✓ 有现货
$19.2 / 个
查看数据手册 →EPM5192AGC84-20
✅ 直接替换✓ 有现货
$41.2 / 个
查看数据手册 →EPM5192AGC-20
✅ 直接替换✓ 有现货
$9.95 / 个
查看数据手册 →EPM5192AGC-15
✅ 直接替换✓ 有现货
$27.8 / 个
查看数据手册 →EPM5192AJI84-15 最大额定值与电气特性
| Device Family | MAX 5000 EPLD |
| Product Type | UV-Erasable / OTP Complex PLD |
| Macrocells | 192 |
| Logic Array Blocks (LABs) | 16 |
| User I/O Pins | 84 |
| Propagation Delay (tPD) | 15 ns |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (nominal 5 V) |
| Process Technology | CMOS EPROM (UV-erasable) |
| Package Type | 84-pin JLCC (J-Leaded Ceramic Chip Carrier) with quartz window |
| 安装类型 | Through-Hole (SMD socket-compatible) |
| 工作温度 | -40 °C to +85 °C (Industrial, 'I' suffix) |
| Programming Method | UV erase + EPROM program via standard Altera programmer |
| Design Tool Support | MAX+PLUS II (legacy); not supported by modern Quartus Prime |
| RoHS 状态 | unknown |
| Lead-Free | unknown |
| 无卤 | unknown |
| Functional Equivalent (Plastic OTP) | EPM5192AJC84-15 (windowless plastic JLCC, same die) |
EPM5192AJI84-15 引脚配置
| 引脚 1 | GND — Ground |
| 引脚 2 | I/O — User I/O pin (bidirectional) |
| 引脚 3 | I/O — User I/O pin (bidirectional) |
| 引脚 4 | I/O — User I/O pin (bidirectional) |
| 引脚 5 | I/O — User I/O pin (bidirectional) |
| 引脚 6 | I/O — User I/O pin (bidirectional) |
| 引脚 7 | I/O — User I/O pin (bidirectional) |
| 引脚 8 | I/O — User I/O pin (bidirectional) |
| 引脚 9 | I/O — User I/O pin (bidirectional) |
| 引脚 10 | I/O — User I/O pin (bidirectional) |
| 引脚 11 | I/O — User I/O pin (bidirectional) |
| 引脚 12 | GND — Ground (multiple GND pins for power distribution) |
| 引脚 13 | I/O — User I/O pin (bidirectional) |
| 引脚 14 | I/O — User I/O pin (bidirectional) |
| 引脚 15 | I/O — User I/O pin (bidirectional) |
| 引脚 16 | I/O — User I/O pin (bidirectional) |
| 引脚 17 | I/O — User I/O pin (bidirectional) |
| 引脚 18 | I/O — User I/O pin (bidirectional) |
| 引脚 19 | I/O — User I/O pin (bidirectional) |
| 引脚 20 | I/O — User I/O pin (bidirectional) |
| 引脚 21 | I/O — User I/O pin (bidirectional) |
| 引脚 22 | I/O — User I/O pin (bidirectional) |
| 引脚 23 | GND — Ground (multiple GND pins for power distribution) |
| 引脚 24 | I/O — User I/O pin (bidirectional) |
| 引脚 25 | I/O — User I/O pin (bidirectional) |
| 引脚 26 | I/O — User I/O pin (bidirectional) |
| 引脚 27 | I/O — User I/O pin (bidirectional) |
| 引脚 28 | I/O — User I/O pin (bidirectional) |
| 引脚 29 | I/O — User I/O pin (bidirectional) |
| 引脚 30 | I/O — User I/O pin (bidirectional) |
| 引脚 31 | I/O — User I/O pin (bidirectional) |
| 引脚 32 | I/O — User I/O pin (bidirectional) |
| 引脚 33 | I/O — User I/O pin (bidirectional) |
| 引脚 34 | GND — Ground (multiple GND pins for power distribution) |
| 引脚 35 | I/O — User I/O pin (bidirectional) |
| 引脚 36 | I/O — User I/O pin (bidirectional) |
| 引脚 37 | I/O — User I/O pin (bidirectional) |
| 引脚 38 | I/O — User I/O pin (bidirectional) |
| 引脚 39 | I/O — User I/O pin (bidirectional) |
| 引脚 40 | I/O — User I/O pin (bidirectional) |
| 引脚 41 | I/O — User I/O pin (bidirectional) |
| 引脚 42 | I/O — User I/O pin (bidirectional) |
| 引脚 43 | I/O — User I/O pin (bidirectional) |
| 引脚 44 | I/O — User I/O pin (bidirectional) |
| 引脚 45 | GND — Ground (multiple GND pins for power distribution) |
| 引脚 46 | I/O — User I/O pin (bidirectional) |
| 引脚 47 | I/O — User I/O pin (bidirectional) |
| 引脚 48 | I/O — User I/O pin (bidirectional) |
| 引脚 49 | I/O — User I/O pin (bidirectional) |
| 引脚 50 | I/O — User I/O pin (bidirectional) |
| 引脚 51 | I/O — User I/O pin (bidirectional) |
| 引脚 52 | I/O — User I/O pin (bidirectional) |
| 引脚 53 | I/O — User I/O pin (bidirectional) |
| 引脚 54 | I/O — User I/O pin (bidirectional) |
| 引脚 55 | I/O — User I/O pin (bidirectional) |
| 引脚 56 | GND — Ground (multiple GND pins for power distribution) |
| 引脚 57 | I/O — User I/O pin (bidirectional) |
| 引脚 58 | I/O — User I/O pin (bidirectional) |
| 引脚 59 | I/O — User I/O pin (bidirectional) |
| 引脚 60 | I/O — User I/O pin (bidirectional) |
| 引脚 61 | I/O — User I/O pin (bidirectional) |
| 引脚 62 | I/O — User I/O pin (bidirectional) |
| 引脚 63 | I/O — User I/O pin (bidirectional) |
| 引脚 64 | I/O — User I/O pin (bidirectional) |
| 引脚 65 | I/O — User I/O pin (bidirectional) |
| 引脚 66 | I/O — User I/O pin (bidirectional) |
| 引脚 67 | GND — Ground (multiple GND pins for power distribution) |
| 引脚 68 | I/O — User I/O pin (bidirectional) |
| 引脚 69 | I/O — User I/O pin (bidirectional) |
| 引脚 70 | I/O — User I/O pin (bidirectional) |
| 引脚 71 | I/O — User I/O pin (bidirectional) |
| 引脚 72 | I/O — User I/O pin (bidirectional) |
| 引脚 73 | I/O — User I/O pin (bidirectional) |
| 引脚 74 | I/O — User I/O pin (bidirectional) |
| 引脚 75 | I/O — User I/O pin (bidirectional) |
| 引脚 76 | I/O — User I/O pin (bidirectional) |
| 引脚 77 | I/O — User I/O pin (bidirectional) |
| 引脚 78 | GND — Ground (multiple GND pins for power distribution) |
| 引脚 79 | I/O — User I/O pin (bidirectional) |
| 引脚 80 | I/O — User I/O pin (bidirectional) |
| 引脚 81 | I/O — User I/O pin (bidirectional) |
| 引脚 82 | VCC — +5 V supply (multiple VCC pins for power distribution) |
| 引脚 83 | VCC — +5 V supply (multiple VCC pins for power distribution) |
| 引脚 84 | VCC — +5 V supply (multiple VCC pins for power distribution) |
典型应用
EPM5192AJI84-15 适用于 6 应用s: Legacy 5V Glue Logic Replacement, Industrial Control & Instrumentation, Telecom Backplane Address Decoding, Microprocessor Peripheral & Bus Controller, Military & Aerospace Prototyping, Field-Replaceable Logic Modules.
Legacy 5V Glue Logic Replacement
The EPM5192AJI84-15 is a drop-in replacement for dozens of 74LS/74F/74AS discrete glue-logic packages in legacy 5 V systems. Its 192 macrocells and 84 I/O pins can absorb 15-25 standard SSI/MSI parts, collapsing board area and improving reliability. Operating from 4.5 V to 5.5 V with industrial -40 °C to +85 °C support, it matches the original TTL supply rail directly without level shifting. Designers port existing schematic-based designs into MAX+PLUS II, then program the chip once. The result is a single PLD replacing a forest of small-scale logic gates with predictable 15 ns propagation delay.
推荐
Industrial Control & Instrumentation
The EPM5192AJI84-15 is well-suited to industrial control PLCs, motor controllers, and process instrumentation where 5 V tolerance, industrial temperature range, and high I/O count are required. Its 84 user I/O pins accommodate many sensor inputs, control outputs, and parallel interface buses in a single chip. The 15 ns tPD enables deterministic logic timing for safety interlocks and sequencing functions. UV-erasable windowed ceramic packaging supports field firmware updates via pull-and-erase cycles. Robust CMOS EPROM technology provides 20+ year data retention - critical for installed industrial systems with long service lives.
推荐
Telecom Backplane Address Decoding
In telecom backplanes and mid-plane bus architectures, the EPM5192AJI84-15 performs multi-card address decoding, interrupt steering, and bus arbitration with predictable 15 ns timing. Its 84 I/O pins handle 16-/32-bit address buses plus control signals in a single device, replacing 5-7 PAL/GAL devices. The 5 V supply tolerance matches legacy backplane rails; -40 °C to +85 °C operation covers outdoor cabinet environments. CMOS EPROM technology provides deterministic logic with no soft-error sensitivity, important for long-term telecom reliability. UV-erasable packaging allows late-stage board bring-up changes.
推荐
Microprocessor Peripheral & Bus Controller
The EPM5192AJI84-15 implements peripheral controllers for 8-bit and 16-bit microprocessors, including chip-select decoders, wait-state generators, interrupt controllers, and bus arbitration logic. With 192 macrocells and 84 I/O, it can implement multiple peripherals in a single chip. The 15 ns propagation delay is comfortable for 8 MHz 8086/68k buses and many 16 MHz 68000-family designs. Industrial temperature range supports embedded computing in factory and vehicle applications. UV-erasable packaging lets engineers iterate on peripheral mappings during prototype development before committing to OTP plastic parts.
推荐
Military & Aerospace Prototyping
The EPM5192AJI84-15 is used in defense and aerospace prototyping where MIL-STD-883 screening and high-reliability packaging are required. Its ceramic JLCC package with quartz window supports MIL-STD-883 Class B screening flows used by Altera/Microsemi for military CPLD programs. 192 macrocells accommodate avionics bus interfaces and control logic; 15 ns tPD suits MIL-STD-1553 and ARINC 429 timing budgets. Industrial -40 °C to +85 °C extends to military temperature ranges when paired with 883B variants. Long-term data retention of CMOS EPROM exceeds 20 years, critical for program-of-record aerospace systems.
推荐
Field-Replaceable Logic Modules
Field-replaceable logic modules in industrial and military systems use the EPM5192AJI84-15 because its UV-erasable ceramic package can be re-programmed multiple times during long service intervals. Maintenance technicians can pull a module, UV-erase the device, and re-program with updated firmware - extending system life without PCB redesign. The 192-macrocell density and 84 I/O support complex control functions on a single chip. 5 V supply tolerance matches legacy system rails; -40 °C to +85 °C operation covers outdoor and industrial environments. Drop-in replacement parts in the same package (EPM5192AJC84-15 plastic OTP) ensure long-term sourcing flexibility.
推荐
推荐产品汇总
工程参考数据： EPM5192AJI84-15 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPM5192AJC84-15 | EPM5192AGC84-15 | EPM5192AJC84-20 | EPM5192AGC84-20 |
|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera |
| Package | 84-pin JLCC (windowed ceramic) | 84-pin JLCC (plastic OTP) - same footprint | 84-pin JLCC - same footprint | 84-pin JLCC - same footprint | 84-pin JLCC - same footprint |
| Macrocells | 192 | 192 | 192 | 192 | 192 |
| User I/O Pins | 84 | 84 | 84 | 84 | 84 |
| Propagation Delay (tPD) | 15 ns | 15 ns | 15 ns | 20 ns | 20 ns |
| Supply Voltage | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V |
| Package Body / Erasability | Ceramic with UV window (erasable) | Plastic, OTP (windowless) | Ceramic with UV window | Plastic, OTP (windowless) | Ceramic with UV window |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
关键差异点
- Windowed ceramic package enables UV erasure and re-programming （对比 EPM5192AJC84-15 (plastic OTP))
- Fastest speed grade in the MAX 5192 family （对比 EPM5192AJI84-20 (20 ns grade))
- Highest-density MAX 5000 PLD with 192 macrocells and 84 I/O （对比 EPM5130 (130 macrocells, 84 I/O) and EPM5064 (64 macrocells, 36 I/O))
设计说明
Modern Quartus Prime (any version) does NOT support the MAX 5000 family. Use Altera MAX+PLUS II version 10.x (BASELINE or higher) for design entry, fitting, and programming file generation. MAX+PLUS II runs only on legacy Windows 9x/NT or in DOSBox emulation. Attempting to import a MAX 5000 design into Quartus will fail at the project-file parse stage. Plan toolchain availability before committing the design.
The 84-pin JLCC socket is a through-hole footprint with J-leads on all four sides; PCB land patterns must match the standard JEDEC JLCC-84 dimensions (1.150 inch body, 0.050 inch pitch). Use a quality machined-pin socket (e.g., 3M Textool or equivalent) so the UV window can be erased without desoldering. Place at least 4 VCC and 4 GND pins with local 0.1 µF decoupling capacitors to suppress switching transients across 192 macrocells.
The MAX 5000 family is end-of-life and not recommended for new designs. For new projects that can absorb a PCB layout change, migrate to a MAX II/MAX V/MAX 10 CPLD supported by current Quartus Prime - for example, the EPM240T100C5N (MAX II, 240 LE, TQFP-100) or 5M80ZE64C5N (MAX V, 80 LE, EQFP-64). These offer lower cost, JTAG-ISP programming, and modern toolchain support while providing similar logic density for typical glue-logic tasks.
合规信息
Legacy Altera EPLD from the 1990s; compliance data not present in verified web sources. RoHS/lead-free status depends on specific date code and factory. 883-screened variants (EPM5130GM883B etc.) are available for military applications requiring full MIL-STD-883 Class B screening.
