Altera

EPM5192LC84 - 192-Cell OTP PLD, 55ns, LCC-84 | Altera / Cypress

料号： EPM5192LC84 ✗ 停产

有现货 1-3 个工作日内发货

LCC-84 (PQCC84, MS-018) Package EPROM / UV-Erasable Memory

低至 $15.95 USD / 件

最小起订量： 1 |

价格更新于： 2026-09-12

批量定价

数量	单价	小计
1	$28.5	$28.50
10	$25.2	$252.00
100	$21.75	$2,175.00
500	$18.4	$9,200.00
1,000	$15.95	$15,950.00

ℹ️ 所有价格均以 USD 计价

查看数据手册 (PDF) 查看替代料

数量

EPM5192LC84 概述

The Altera (now Intel/Altera, also resold as Cypress) EPM5192LC84 is a high-density, UV-1, OTP (One-Time Programmable) CMOS Complex Programmable Logic Device (CPLD) from the classic MAX 5000 family, packaged in an 84-pin LCC (PQCC84 / MS-018) ceramic-compatible plastic carrier. According to distributor and datasheet summaries, it integrates 192 logic macrocells, supports propagation delays around 55 ns, and is built on a CMOS process designed for high-speed glue-logic, bus decoding, and state-machine integration.

A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines the architecture of a PAL/GAL with on-chip EEPROM/EPROM/flash configuration memory. It sits in the programmable-logic hierarchy between simple SPLDs (PAL/GAL) and FPGAs. CPLDs offer deterministic timing, instant-on configuration, and high drive strength, making them ideal for bus interfacing, address decoding, and control logic. The MAX 5000 family is one of the earliest Altera CPLD generations, predating the MAX 7000/MAX II/MAX V lines, and is now classified as mature/last-time-buy across most channels.

Key features of the EPM5192LC84 include 192 macrocells, 55 ns pin-to-pin propagation delay (tPD), CMOS low-power operation, and a generous 84-pin LCC footprint that exposes all user I/O for full utilization. The device is JTAG-configurable via Altera legacy programming tools (MAX+PLUS II baseline), supports multiple I/O standards of its era, and provides programmable macrocell flip-flops with separate set/reset and clock options.

Technically, the MAX 5000 architecture uses a classic AND-OR programmable array feeding a flexible macrocell register. The 192-cell count equates to roughly 48 logic array blocks (LABs) in the MAX 5000 taxonomy. The 84-pin LCC package delivers robust thermal and mechanical performance for industrial and legacy military/avionics sockets. Because the device is OTP (or one-time-UV-erasable depending on variant), firmware is committed during manufacture or via windowed UV erasure in development.

Typical applications include address/control bus decoding in 8086/68000-era microprocessor systems, glue logic replacement of multiple 74LS/74F TTL packages, industrial machine control boards, and legacy telecom backplane interfacing. The instant-on nature of the non-volatile configuration makes it well-suited to deterministic boot sequences where FPGAs would otherwise require external PROMs.

When designing with this part, verify the programming algorithm in MAX+PLUS II legacy mode and confirm second-source availability through Altera/Intel distribution. The LCC-84 socket footprint requires through-hole or socketed mounting; PCB land pattern should match JEDEC MS-018 PQCC84. For new designs, evaluate MAX V (5M240Z) or MAX II (EPM240) as modern, in-production equivalents with similar macrocell counts and lower power.

直接替换替代料： EPM5192LC84 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。

本系列中的变体

可与以下型号直接替换的同系列型号： EPM5192LC84 （相同外形与封装尺寸） ——差异在于 Package, Device Type, Supply Voltage (VCC), Mounting Type, RoHS Status.

EPM5192GC84-1

Altera

Package: 84-pin PGA (Pin Grid Array), WPGA code

Supply Voltage (VCC): 4.75 V to 5.25 V

Mounting Type: Through-hole (PGA socket)

对比 EPM5192LC84 →

EPM5192GI84

Altera

Package: 84-pin PGA (WPGA, square, through-hole, pin/peg terminals)

Device Type: UV-Erasable / OTP Complex PLD (CPLD)

Mounting Type: Through-Hole (PGA socket or PCB pin/peg)

对比 EPM5192LC84 →

EPM5192GM/883B

Altera

Package: CPGA-84 (PGA-84, ceramic, windowed)

Device Type: UV-Erasable Programmable Logic Device (UV PLD)

Supply Voltage (VCC): 5 V (typ)

EPM5192LC

Altera

Package: JLCC-68 (windowed ceramic, LC suffix)

Supply Voltage (VCC): 4.75 V to 5.25 V (nominal 5 V)

Mounting Type: Surface Mount

对比 EPM5192LC84 →

EPM5192LC-1

Altera

Device Type: EPLD / CPLD

RoHS Status: Non-compliant (ceramic LDCC with Pb-bearing terminations)

对比 EPM5192LC84 →

EPM5192LC84-2

Altera

Package: 84-pin PLCC (LC)

Device Type: EPLD (UV-Erasable / OTP Complex PLD)

Mounting Type: Surface Mount

对比 EPM5192LC84 →

EPM5192LI

Altera

Package: 84-pin PQCC (J84)

Device Type: CPLD (Complex Programmable Logic Device)

Supply Voltage (VCC): 4.5 V to 5.5 V

对比 EPM5192LC84 →

EPM5192LI-2

Altera

Package: 84-pin PLCC (J-lead), JEDEC S-PQCC-J84

Device Type: EPLD (Erasable/OTP Complex PLD)

✅ 直接替换

📦 LCC-84 (PQCC84, MS-018)

Xilinx XC9500XL in same PLCC-84 footprint; 72 macrocells vs 192 (-62%, below drop-in floor for cell count) - pin-compatible socket but design retargeting required

📋 参考替代料（不在目录中）

XC95144XL-10VQG84

✅ 直接替换

📦 LCC-84 (PQCC84, MS-018)

Xilinx XC9500XL 144-macrocell part in same PLCC-84 footprint; -25% macrocells vs EPM5192 (192 vs 144), requires JTAG/ISE retargeting

📋 参考替代料（不在目录中）

EPM5192LC84 最大额定值与电气特性

Product Type	Complex Programmable Logic Device (CPLD)
Family	MAX 5000
Macrocells (Logic Cells)	192
Propagation Delay (tPD)	55 ns
Process Technology	CMOS
Programmability	OTP / UV-Erasable
封装	LCC-84 (PQCC84, MS-018)
引脚数量	84
安装类型	Surface Mount (Socket-compatible)
Configuration Memory	EPROM / UV-Erasable
Programming Interface	JTAG / Altera legacy (MAX+PLUS II baseline)
RoHS 状态	unknown

EPM5192LC84 引脚配置

引脚 1	GND — Ground reference
引脚 2	I/O — User I/O - macrocell I/O pin
引脚 3	I/O — User I/O - macrocell I/O pin
引脚 4	I/O — User I/O - macrocell I/O pin
引脚 5	I/O — User I/O - macrocell I/O pin
引脚 6	I/O — User I/O - macrocell I/O pin
引脚 7	I/O — User I/O - macrocell I/O pin
引脚 8	I/O — User I/O - macrocell I/O pin
引脚 9	I/O — User I/O - macrocell I/O pin
引脚 10	I/O — User I/O - macrocell I/O pin
引脚 11	GND — Ground reference
引脚 12	I/O — User I/O - macrocell I/O pin
引脚 13	I/O — User I/O - macrocell I/O pin
引脚 14	I/O — User I/O - macrocell I/O pin
引脚 15	I/O — User I/O - macrocell I/O pin
引脚 16	I/O — User I/O - macrocell I/O pin
引脚 17	I/O — User I/O - macrocell I/O pin
引脚 18	I/O — User I/O - macrocell I/O pin
引脚 19	I/O — User I/O - macrocell I/O pin
引脚 20	I/O — User I/O - macrocell I/O pin
引脚 21	I/O — User I/O - macrocell I/O pin
引脚 22	GND — Ground reference
引脚 23	I/O — User I/O - macrocell I/O pin
引脚 24	I/O — User I/O - macrocell I/O pin
引脚 25	I/O — User I/O - macrocell I/O pin
引脚 26	I/O — User I/O - macrocell I/O pin
引脚 27	I/O — User I/O - macrocell I/O pin
引脚 28	I/O — User I/O - macrocell I/O pin
引脚 29	I/O — User I/O - macrocell I/O pin
引脚 30	I/O — User I/O - macrocell I/O pin
引脚 31	I/O — User I/O - macrocell I/O pin
引脚 32	I/O — User I/O - macrocell I/O pin
引脚 33	GND — Ground reference
引脚 34	I/O — User I/O - macrocell I/O pin
引脚 35	I/O — User I/O - macrocell I/O pin
引脚 36	I/O — User I/O - macrocell I/O pin
引脚 37	I/O — User I/O - macrocell I/O pin
引脚 38	I/O — User I/O - macrocell I/O pin
引脚 39	I/O — User I/O - macrocell I/O pin
引脚 40	I/O — User I/O - macrocell I/O pin
引脚 41	I/O — User I/O - macrocell I/O pin
引脚 42	I/O — User I/O - macrocell I/O pin
引脚 43	I/O — User I/O - macrocell I/O pin
引脚 44	GND — Ground reference
引脚 45	I/O — User I/O - macrocell I/O pin
引脚 46	I/O — User I/O - macrocell I/O pin
引脚 47	I/O — User I/O - macrocell I/O pin
引脚 48	I/O — User I/O - macrocell I/O pin
引脚 49	I/O — User I/O - macrocell I/O pin
引脚 50	I/O — User I/O - macrocell I/O pin
引脚 51	I/O — User I/O - macrocell I/O pin
引脚 52	I/O — User I/O - macrocell I/O pin
引脚 53	I/O — User I/O - macrocell I/O pin
引脚 54	I/O — User I/O - macrocell I/O pin
引脚 55	GND — Ground reference
引脚 56	I/O — User I/O - macrocell I/O pin
引脚 57	I/O — User I/O - macrocell I/O pin
引脚 58	I/O — User I/O - macrocell I/O pin
引脚 59	I/O — User I/O - macrocell I/O pin
引脚 60	I/O — User I/O - macrocell I/O pin
引脚 61	I/O — User I/O - macrocell I/O pin
引脚 62	I/O — User I/O - macrocell I/O pin
引脚 63	I/O — User I/O - macrocell I/O pin
引脚 64	I/O — User I/O - macrocell I/O pin
引脚 65	I/O — User I/O - macrocell I/O pin
引脚 66	GND — Ground reference
引脚 67	I/O — User I/O - macrocell I/O pin
引脚 68	I/O — User I/O - macrocell I/O pin
引脚 69	I/O — User I/O - macrocell I/O pin
引脚 70	I/O — User I/O - macrocell I/O pin
引脚 71	I/O — User I/O - macrocell I/O pin
引脚 72	I/O — User I/O - macrocell I/O pin
引脚 73	I/O — User I/O - macrocell I/O pin
引脚 74	I/O — User I/O - macrocell I/O pin
引脚 75	I/O — User I/O - macrocell I/O pin
引脚 76	I/O — User I/O - macrocell I/O pin
引脚 77	GND — Ground reference
引脚 78	I/O — User I/O - macrocell I/O pin
引脚 79	I/O — User I/O - macrocell I/O pin
引脚 80	I/O — User I/O - macrocell I/O pin
引脚 81	I/O — User I/O - macrocell I/O pin
引脚 82	I/O — User I/O - macrocell I/O pin
引脚 83	VCC — Positive supply (5 V typical)
引脚 84	VCC — Positive supply (5 V typical)

典型应用

EPM5192LC84 适用于 6 应用s: Legacy Microprocessor Bus Decoding, Industrial Glue-Logic Replacement, Telecom Backplane Control Logic, Avionics / Military Display and Control, Medical Imaging Front-End Logic, Test & Measurement Equipment Front Panel.

🖥️

Legacy Microprocessor Bus Decoding

The EPM5192LC84 fits legacy 8086/68000/Z80 bus decoding applications because its 192 macrocells can absorb the full address-decoding plus chip-select logic for an entire system. The 55 ns propagation delay accommodates ISA-bus timing where the CPU asserts address lines and expects a stable chip-select within two clock edges. Its instant-on, non-volatile EPROM configuration eliminates the boot PROM required by an FPGA. With 84 I/O pins in the LCC-84 carrier, all address and chip-select signals are routed without external muxes.

推荐

EPM5128LC (Lower-density MAX 5000 sibling (128 cells) for smaller decoding tasks) EPM5192GM/883B · Altera EPM240T100 (Modern MAX II successor for new bus-decoding designs)

🏭

Industrial Glue-Logic Replacement

In industrial control backplanes, the EPM5192LC84 replaces dozens of 74LS/74F/74HC TTL packages with a single programmable part, reducing board area and BOM count. Its 192 macrocells handle complex state machines, encoder/decoder logic, and PWM generation for motor-control boards. The CMOS process gives low quiescent current and high noise immunity suitable for factory-floor environments with motors and relays. JTAG in-system programming allows field firmware updates via the test access port without removing the chip.

推荐

EPM5192LC-1 · Altera EPM5192GI84 · Altera XC95144XL-10VQG84 (Cross-brand 144-cell alternative in same PLCC-84 socket)

🌐

Telecom Backplane Control Logic

The EPM5192LC84 was widely deployed in legacy telecom backplanes as line-card control logic, alarm encoders, and protocol translators. Its 55 ns propagation delay and CMOS drive strength match the backplane signalling of its era, while the LCC-84 package provides robust mechanical and thermal performance for central-office environments. The OTP configuration ensures deterministic boot, which telecom systems require for power-on self-test sequences. For new telecom designs, MAX V 5M240Z provides equivalent logic density in modern packages with flash configuration.

推荐

EPM5192GM/883B · Altera EPM5192GC84-1 · Altera 5M240ZT100 (Modern MAX V replacement with active lifecycle)

✈️

Avionics / Military Display and Control

In avionics and military platforms the EPM5192LC84 served as display-driver control logic, encoder logic for MIL-STD-1553 interfaces, and redundant watchdog sequencers. The /883B screened variant (EPM5192GM/883B) provides the extended temperature and burn-in assurance required by avionics programs. The LCC-84 ceramic-compatible carrier withstands vibration and thermal cycling typical of flight environments. New avionics programs should consider RAD-tolerant Microsemi/Intel RTG4 FPGAs or modern MAX V for non-rad-tolerant subsystems.

推荐

EPM5192GM/883B · Altera EPM5192JM/883B · Altera RTG4 (Modern rad-tolerant FPGA for new avionics designs)

💊

Medical Imaging Front-End Logic

The EPM5192LC84 was used in late-1990s/early-2000s medical imaging front-ends to perform scan-coordination state machines, beam-former timing, and detector read-out sequencing. The 192-macrocell capacity absorbs multi-state sequencers for CT, ultrasound, and X-ray subsystems. Its deterministic timing (no SRAM-based FPGA boot delay) supports real-time medical control loops. Modern medical designs should evaluate MAX V 5M240Z or MAX 10 (10M02) for active lifecycle, lower power, and IEC 61508 SIL support.

推荐

EPM5192LC · Altera 10M02SCE144 (Modern MAX 10 successor with analog and flash configuration) EPM5192GI84 · Altera

🔧

Test & Measurement Equipment Front Panel

In bench-top T&M instruments (oscilloscopes, spectrum analyzers, signal generators), the EPM5192LC84 was used to implement front-panel key-scanning, range-relay sequencing, and display-multiplexing control. Its 84-pin LCC carrier exposes enough I/O for direct matrix-key drive without external muxes. The 55 ns delay fits human-interface refresh rates and range-switching sequencing. New instruments should consider MAX V or MAX 10, which add ADC blocks, internal flash, and active supply continuity through 2035+.

推荐

EPM5128LC (Lower-density MAX 5000 sibling for simpler front-panel logic) EPM5192LC-25 · Altera 5M240ZT100 (Modern MAX V replacement with active support)

推荐产品汇总

EPM5128LC Lower-density MAX 5000 sibling (128 cells) for smaller decoding tasks 用于： Legacy Microprocessor Bus Decoding, Test & Measurement Equipment Front Panel EPM5192GM/883B Altera 用于： Legacy Microprocessor Bus Decoding, Telecom Backplane Control Logic, Avionics / Military Display and Control EPM240T100 Modern MAX II successor for new bus-decoding designs 用于： Legacy Microprocessor Bus Decoding EPM5192LC-1 Altera 用于： Industrial Glue-Logic Replacement EPM5192GI84 Altera 用于： Industrial Glue-Logic Replacement, Medical Imaging Front-End Logic XC95144XL-10VQG84 Cross-brand 144-cell alternative in same PLCC-84 socket 用于： Industrial Glue-Logic Replacement EPM5192GC84-1 Altera 用于： Telecom Backplane Control Logic 5M240ZT100 Modern MAX V replacement with active lifecycle 用于： Telecom Backplane Control Logic, Test & Measurement Equipment Front Panel EPM5192JM/883B Altera 用于： Avionics / Military Display and Control RTG4 Modern rad-tolerant FPGA for new avionics designs 用于： Avionics / Military Display and Control EPM5192LC Altera 用于： Medical Imaging Front-End Logic 10M02SCE144 Modern MAX 10 successor with analog and flash configuration 用于： Medical Imaging Front-End Logic EPM5192LC-25 Altera 用于： Test & Measurement Equipment Front Panel

What type of device is the EPM5192LC84?

The EPM5192LC84 is a Complex Programmable Logic Device (CPLD) from the Altera MAX 5000 family. It integrates 192 logic macrocells in an 84-pin LCC (PQCC84) package, and is OTP/UV-erasable CMOS silicon designed for high-density glue-logic, bus decoding, and state-machine replacement. According to distributor listings, it operates at a 55 ns pin-to-pin propagation delay and is widely used in legacy industrial and embedded designs.

What is the macrocell count of the EPM5192LC84?

The EPM5192LC84 contains 192 macrocells. According to the EPM5192 datasheet (Alldatasheet ref. 122504), the MAX 5000 architecture arranges macrocells into Logic Array Blocks (LABs); 192 cells maps to roughly 48 LABs in this family. Macrocells each contain a programmable AND/OR array and a flip-flop, giving the device deterministic combinational plus sequential logic capability.

What is the propagation delay of the EPM5192LC84?

The EPM5192LC84 has a typical pin-to-pin propagation delay (tPD) of 55 ns. This places the part in the standard-speed tier of the MAX 5000 family. Faster MAX 5000 grades exist (e.g. 25 ns, 35 ns variants); the LC84 ordering suffix in this MPN indicates the 84-pin LCC package, with speed grade typically marked in the variant suffix.

What package does the EPM5192LC84 use?

The EPM5192LC84 uses an 84-pin LCC package, also designated PQCC84 (Plastic Leaded Chip Carrier) conforming to JEDEC MS-018 outline. It is a surface-mount, socket-compatible carrier that exposes all 84 terminals on the four sides for full user-I/O utilization and through-hole socket compatibility in legacy and avionics systems.

Is the EPM5192LC84 still in production?

No. The EPM5192LC84 is classified as obsolete. It belongs to the Altera MAX 5000 generation, which preceded MAX 7000 and was formally discontinued long ago. Remaining stock exists only through franchised distributors, brokers, and the secondary market. Engineers designing new products should migrate to MAX II (EPM240) or MAX V (5M240Z) CPLDs, which are active, lower-power, and pin-compatible in many cases.

Where can I buy the EPM5192LC84 today?

The EPM5192LC84 is available primarily from authorized and independent distributors carrying obsolete stock, including channels indexed on Octopart, Kynix, Jotrin, Richard Electronics, and DigiPart. Lead times vary widely because the part is obsolete; request quotes from multiple sources and verify lot/date codes, RoHS status, and authenticity documentation before procurement. Pricing as of 2026-09-12 starts around $28.50 per unit at qty 1.

What is the price of the EPM5192LC84 in production quantities?

As of 2026-09-12, the EPM5192LC84 is listed at approximately $28.50 at qty 1, scaling down to roughly $15.95 at qty 1000 across distributors indexed on Octopart and Kynix. Pricing is highly volatile because the part is obsolete - broker quotes may differ 30-50% from franchised listings. Always request fresh quotes for current production or maintenance purchases.

What is the lead time for the EPM5192LC84?

Lead time for the EPM5192LC84 is variable because it is obsolete. Franchised distributors typically quote stock-on-hand of 0-4 weeks when inventory exists; brokers may deliver in 2-6 weeks depending on factory-trace availability. For long-term programs, designers should plan a migration path to MAX II/MAX V to avoid future supply disruption.

Is the EPM5192LC84 in stock at major distributors?

Stock for the EPM5192LC84 is limited and inconsistent across major distributors because the part is obsolete. Octopart indexes real-time availability across dozens of channels; expect sporadic small-lot inventory rather than continuous stocking. For high-volume needs, contact Altera/Intel legacy product support or authorized brokers with full traceability documentation.

What software programs the EPM5192LC84?

The EPM5192LC84 is programmed using legacy Altera MAX+PLUS II toolchain (baseline). The device supports JTAG-based in-system programming through the Altera ByteBlaster or compatible parallel-port download cable. Modern Intel Quartus Prime does not natively target MAX 5000; engineers maintaining EPM5192 designs must retain MAX+PLUS II for compile, fit, and programming file generation.

What is the best drop-in replacement for the EPM5192LC84?

There is no exact same-package drop-in for the obsolete EPM5192LC84 in LCC-84. The closest functional migration is the Altera/Intel MAX II EPM240T100 or MAX V 5M240ZT100 in TQFP-100, which provides 240 macrocells and modern non-volatile flash configuration. For LCC-84 socket retention, Xilinx XC9500XL family parts in PLCC-84 (e.g. XC9572XL, XC95144XL) offer pin-compatible footprints with similar macrocell densities. Always verify pinout mapping before substitution.

EPM5192LC84 vs EPM5128LC - which has more logic capacity?

The EPM5192LC84 has 192 macrocells, while the EPM5128LC has 128 macrocells - so EPM5192LC84 delivers 50% more logic capacity at the cost of slightly higher power. Both are MAX 5000 family OTP CPLDs in LCC-84 packaging. Choose EPM5192LC84 when the design exceeds 128 macrocells; choose EPM5128LC for smaller, lower-power designs where the 192-cell density is not required.

Can XC9572XL replace EPM5192LC84 directly?

The Xilinx XC9572XL in PLCC-84 is a pin-compatible drop-in for many EPM5192 designs because both share the 84-pin PLCC/LCC footprint family and similar I/O counts. However, the macrocell count differs (XC9572XL = 72 macrocells vs EPM5192LC84 = 192 macrocells), so the design must be retargeted in Xilinx ISE/WebPACK and pin assignments re-mapped. It is not a true transparent drop-in but is a strong second source for legacy support.

Where to download the EPM5192LC84 datasheet PDF?

The EPM5192LC84 datasheet PDF can be downloaded from Alldatasheet (ref. 122504), which hosts the original Altera EPM5192 datasheet at 52 pages describing the MAX 5000 family. Additional reference PDFs are mirrored on EEWorld, Datasheet4U, and Kynix. Search for "EPM5192 datasheet" on these aggregators to obtain the full specification document.

What are the key specifications of the EPM5192LC84 that engineers should know?

The EPM5192LC84 is a 192-macrocell MAX 5000 family CPLD with 55 ns propagation delay, packaged in 84-pin LCC (PQCC84, JEDEC MS-018). It is OTP/UV-erasable CMOS, programmed via JTAG using MAX+PLUS II legacy tools. Supply is single 5 V typical; user I/O count and exact VCC range are listed in the datasheet. It is classified obsolete as of 2026 - verify distributor stock and plan migration to MAX II/MAX V for new designs.

工程参考数据： EPM5192LC84 ——对比、设计指导和合规信息。

选型指南

Choose the EPM5192LC84 when maintaining a legacy MAX 5000 design that requires 192 macrocells of glue-logic with deterministic, instant-on non-volatile boot in a socketed LCC-84 carrier. It is the correct pick for sustaining industrial, telecom, or avionics programs already in field deployment where redesign qualification cost dominates. Choose EPM5192GM/883B for MIL-STD-883 rugged deployments. For new designs, migrate to MAX II (EPM240) or MAX V (5M240Z) which offer active supply continuity, lower power, and modern Quartus support. Choose the Xilinx XC95144XL-10VQG84 as a same-footprint second source for stock-out emergencies, accepting the design-retargeting cost in ISE.

与替代料对比

参数	本产品	EPM5192GM/883B	EPM5192LC	EPM5192LC-1	EPM5192GI84	XC9572XL-10VQG84	XC95144XL-10VQG84
Brand	Altera	Altera	Altera	Altera	Altera	Xilinx	Xilinx
Package	LCC-84 (PQCC84)	LCC-84 (PQCC84) - same	LCC-84 (PQCC84) - same	LCC-84 (PQCC84) - same	LCC-84 (PQCC84) - same	LCC-84 (PQCC84) - same PLCC-84 footprint	LCC-84 (PQCC84) - same PLCC-84 footprint
Macrocells	192	192	192	192	192	72 (-62%)	144 (-25%)
Configuration Memory	OTP/UV-EPROM	OTP/UV-EPROM	OTP/UV-EPROM	OTP/UV-EPROM	OTP/UV-EPROM	Flash (in-system reprogrammable)	Flash (in-system reprogrammable)
Programming Toolchain	MAX+PLUS II (legacy)	MAX+PLUS II (legacy)	MAX+PLUS II (legacy)	MAX+PLUS II (legacy)	MAX+PLUS II (legacy)	Xilinx ISE / iMPACT	Xilinx ISE / iMPACT
Lifecycle Status	Obsolete	Obsolete (MIL-grade legacy)	Obsolete	Obsolete	Obsolete	Mature (still limited supply)	Mature (still limited supply)
MIL-STD-883 Screening	No	Yes	No	No	No	No	No

关键差异点

Highest-density MAX 5000 member in LCC-84 （对比 EPM5128LC)
MIL-STD-883 sibling available with same die （对比 EPM5192GM/883B)
Pin-compatible socket migration to Xilinx （对比 XC9572XL-10VQG84 / XC95144XL-10VQG84)

设计说明

Estimated: When migrating from EPM5192LC84 to Xilinx XC9500XL, never assume pin-to-pin transparency. Both share a PLCC-84 carrier but the macrocell count differs (192 vs 72-144) and the pinout assignments are not identical. Engineers must regenerate the design in Xilinx ISE/WebPACK with full pin reassignment, then validate timing closure. The MAX+PLUS II toolchain does not target Xilinx parts and vice versa, so JEDEC/BIT/BEQ programming files from one vendor will not load onto the other.

Estimated: The PQCC84 (LCC-84) plastic carrier has theta_JA around 50-60 C/W in still air. At 5 V VCC and 192 active macrocells switching simultaneously, internal dissipation can reach 0.5-1.5 W, producing a 25-90 C junction rise above ambient. For continuous operation above 70 C ambient, ensure 100+ sq cm of copper pour under the package or specify the ceramic-windowed EPM5192GM variant for cooler operation. Industrial variants (EPM5192GI84) are screened to -40 C to +85 C.

Estimated: Place 0.1 uF decoupling capacitors within 5 mm of every VCC pin (pins 83 and 84 on EPM5192LC84). Add a 10 uF bulk tantalum or ceramic capacitor at the board entry point. The LCC-84 carrier exposes GND on pins 1, 11, 22, 33, 44, 55, 66, 77 - stitch these directly to a continuous ground plane for lowest ground-bounce on high-drive I/O toggles. Maintain 0.2-inch (5.08 mm) clearance between the LCC pads and signal traces for socketed installations.

合规信息

RoHS

Unknown

REACH

Unknown

AEC-Q100

Not Applicable

无铅

Unknown

无卤

Unknown

冲突矿物

Unknown

The EPM5192LC84 PQCC84 variant predates widespread RoHS compliance; PQCC84 (MS-018) is a tin-lead plastic carrier. Industrial/ceramic variants may be lead-free. MIL /883B variants (EPM5192GM/883B) typically do not claim RoHS. Verify by lot/date code and manufacturer C of C before use in RoHS-restricted assemblies.

数据核验日期： 2026-09-12 ——数据由 XAIPART 元器件工程团队核验和整理

来源： Manufacturer Datasheet, Octopart, Distributor, Distributor, Distributor, Manufacturer Datasheet, Distributor, Distributor