EPM7256EQC160-12 - MAX 7000 CPLD, 256 Macrocells, 12ns, PQFP-160
料号： EPM7256EQC160-12 ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.2 | $252.00 |
| 100 | $21.8 | $2,180.00 |
| 500 | $19.4 | $9,700.00 |
| 1,000 | $17.1 | $17,100.00 |
EPM7256EQC160-12 概述
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like logic blocks (called Logic Array Blocks, or LABs) on a single chip, connected through a programmable interconnect matrix. CPLDs sit between simple SPLDs (PAL/GAL) and FPGAs in the programmable logic hierarchy, offering predictable timing, low power, and fast I/O-to-I/O propagation delays. The MAX 7000 family was Altera's second-generation EEPROM-based CPLD architecture and is widely used for glue-logic, bus interfacing, address decoding, and control state-machine replacement.
Key features of the EPM7256EQC160-12 include 16 Logic Array Blocks, 256 macrocells, 132 I/O pins, in-system programmability via JTAG, and 5 V tolerant I/O with 3.3 V compatibility. The device delivers up to 90.9 MHz maximum operating frequency with a 12 ns tPD, making it well suited for legacy 5 V system designs. Its non-volatile EEPROM configuration cell means the part retains its logic implementation across power cycles without external boot memory.
The MAX 7000 architecture is based on a sum-of-products logic array with macrocell flip-flops, programmable interconnect, and per-pin output enable control. With 16 LABs of 16 macrocells each, the part provides 256 flip-flops for sequential logic. Programmable interconnect delay is fixed (unlike FPGA routing), giving deterministic, predictable timing that simplifies static timing analysis in control and interface designs.
Typical applications include 5 V system glue logic, address decoding for microprocessors and DSPs, bus interfacing (ISA, PCI, VME), state-machine replacement, industrial control boards, and telecom infrastructure requiring non-volatile fast-turn-on logic. The 132 I/O count makes it a useful integration point for peripheral bridging in legacy designs.
When designing with this part, note that it is part of the mature MAX 7000 family: most PCBs that used it can drop in faster speed grades (-7, -10) or temperature-extended variants (-15I, -20) provided the package and pinout match. Designers should consult the Quartus/MAX+PLUS II support notes for legacy software compatibility. This page combines distributor pricing, drop-in alternative cross-references, and practical design guidance not found in the original datasheet.
直接替换替代料： EPM7256EQC160-12 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPM7256EQC160-12 （相同外形与封装尺寸） ——差异在于 Mounting Type, Operating Temperature, RoHS Status.
快速对比工具——选择替代料号进行并排对比：
EPM7256EQC160-15
✅ 直接替换📋 参考替代料（不在目录中）
EPM7256EQC160-10
✅ 直接替换📋 参考替代料（不在目录中）
EPM7256EQC160-12P
✅ 直接替换📋 参考替代料（不在目录中）
EPM7256EQC160-15N
✅ 直接替换📋 参考替代料（不在目录中）
EPM7256EGC192-12
✅ 直接替换✓ 有现货
$17.85 / 个
查看数据手册 →EPM7256EQC160-12 最大额定值与电气特性
| Family | MAX 7000 |
| Programmable Type | EE PLD (CPLD, in-system programmable EEPROM) |
| Number of Macrocells | 256 |
| Number of Logic Blocks / LABs | 16 |
| Number of Gates | 5,000 usable gates |
| Number of I/O Pins | 132 |
| Propagation Delay tPD (max) | 12 ns |
| Maximum Operating Frequency | 90.9 MHz |
| Supply Voltage VCCINT | 4.75 V to 5.25 V |
| I/O Standard | 5 V TTL, 3.3 V compatible |
| 工作温度 | 0 °C to 70 °C (Commercial) |
| 封装 / 外壳 | 160-pin PQFP (28 × 28 mm) |
| 安装类型 | Surface Mount |
| Process Technology | CMOS EEPROM |
| Programming Interface | JTAG (IEEE 1532 / IEEE 1149.1) |
| RoHS 状态 | Compliant (lead-free PQFP) |
| 生命周期状态 | Obsolete |
EPM7256EQC160-12 引脚配置
| 引脚 1 | I/O — User I/O pin (function depends on user design) |
| 引脚 2 | I/O — User I/O pin |
| 引脚 3 | I/O — User I/O pin |
| 引脚 4 | I/O — User I/O pin |
| 引脚 5 | I/O — User I/O pin |
| 引脚 6 | I/O — User I/O pin |
| 引脚 7 | GND — Ground |
| 引脚 8 | I/O — User I/O pin |
| 引脚 9 | I/O — User I/O pin |
| 引脚 10 | I/O — User I/O pin |
| 引脚 11 | I/O — User I/O pin |
| 引脚 12 | I/O — User I/O pin |
| 引脚 13 | I/O — User I/O pin |
| 引脚 14 | I/O — User I/O pin |
| 引脚 15 | TDI — JTAG Test Data In (IEEE 1149.1) |
| 引脚 16 | I/O — User I/O pin |
| 引脚 17 | I/O — User I/O pin |
| 引脚 18 | I/O — User I/O pin |
| 引脚 19 | I/O — User I/O pin |
| 引脚 20 | I/O — User I/O pin |
| 引脚 21 | I/O — User I/O pin |
| 引脚 22 | I/O — User I/O pin |
| 引脚 23 | I/O — User I/O pin |
| 引脚 24 | I/O — User I/O pin |
| 引脚 25 | GND — Ground |
| 引脚 26 | I/O — User I/O pin |
| 引脚 27 | I/O — User I/O pin |
| 引脚 28 | I/O — User I/O pin |
| 引脚 29 | I/O — User I/O pin |
| 引脚 30 | I/O — User I/O pin |
| 引脚 31 | I/O — User I/O pin |
| 引脚 32 | I/O — User I/O pin |
| 引脚 33 | VCC — 5 V supply |
| 引脚 34 | I/O — User I/O pin |
| 引脚 35 | I/O — User I/O pin |
| 引脚 36 | I/O — User I/O pin |
| 引脚 37 | I/O — User I/O pin |
| 引脚 38 | I/O — User I/O pin |
| 引脚 39 | I/O — User I/O pin |
| 引脚 40 | I/O — User I/O pin |
| 引脚 41 | TMS — JTAG Test Mode Select |
| 引脚 42 | I/O — User I/O pin |
| 引脚 43 | I/O — User I/O pin |
| 引脚 44 | I/O — User I/O pin |
| 引脚 45 | I/O — User I/O pin |
| 引脚 46 | I/O — User I/O pin |
| 引脚 47 | I/O — User I/O pin |
| 引脚 48 | I/O — User I/O pin |
| 引脚 49 | I/O — User I/O pin |
| 引脚 50 | I/O — User I/O pin |
| 引脚 51 | GND — Ground |
| 引脚 52 | I/O — User I/O pin |
| 引脚 53 | I/O — User I/O pin |
| 引脚 54 | I/O — User I/O pin |
| 引脚 55 | I/O — User I/O pin |
| 引脚 56 | I/O — User I/O pin |
| 引脚 57 | I/O — User I/O pin |
| 引脚 58 | I/O — User I/O pin |
| 引脚 59 | TCK — JTAG Test Clock |
| 引脚 60 | I/O — User I/O pin |
| 引脚 61 | I/O — User I/O pin |
| 引脚 62 | I/O — User I/O pin |
| 引脚 63 | I/O — User I/O pin |
| 引脚 64 | I/O — User I/O pin |
| 引脚 65 | I/O — User I/O pin |
| 引脚 66 | I/O — User I/O pin |
| 引脚 67 | I/O — User I/O pin |
| 引脚 68 | I/O — User I/O pin |
| 引脚 69 | VCC — 5 V supply |
| 引脚 70 | I/O — User I/O pin |
| 引脚 71 | I/O — User I/O pin |
| 引脚 72 | I/O — User I/O pin |
| 引脚 73 | I/O — User I/O pin |
| 引脚 74 | I/O — User I/O pin |
| 引脚 75 | I/O — User I/O pin |
| 引脚 76 | I/O — User I/O pin |
| 引脚 77 | TDO — JTAG Test Data Out |
| 引脚 78 | I/O — User I/O pin |
| 引脚 79 | I/O — User I/O pin |
| 引脚 80 | I/O — User I/O pin |
| 引脚 81 | I/O — User I/O pin |
| 引脚 82 | I/O — User I/O pin |
| 引脚 83 | I/O — User I/O pin |
| 引脚 84 | I/O — User I/O pin |
| 引脚 85 | I/O — User I/O pin |
| 引脚 86 | GND — Ground |
| 引脚 87 | I/O — User I/O pin |
| 引脚 88 | I/O — User I/O pin |
| 引脚 89 | I/O — User I/O pin |
| 引脚 90 | I/O — User I/O pin |
| 引脚 91 | I/O — User I/O pin |
| 引脚 92 | I/O — User I/O pin |
| 引脚 93 | I/O — User I/O pin |
| 引脚 94 | I/O — User I/O pin |
| 引脚 95 | I/O — User I/O pin |
| 引脚 96 | I/O — User I/O pin |
| 引脚 97 | VCC — 5 V supply |
| 引脚 98 | I/O — User I/O pin |
| 引脚 99 | I/O — User I/O pin |
| 引脚 100 | I/O — User I/O pin |
| 引脚 101 | I/O — User I/O pin |
| 引脚 102 | I/O — User I/O pin |
| 引脚 103 | I/O — User I/O pin |
| 引脚 104 | I/O — User I/O pin |
| 引脚 105 | OE1 — Global Output Enable 1 (active low) |
| 引脚 106 | I/O — User I/O pin |
| 引脚 107 | I/O — User I/O pin |
| 引脚 108 | I/O — User I/O pin |
| 引脚 109 | I/O — User I/O pin |
| 引脚 110 | I/O — User I/O pin |
| 引脚 111 | I/O — User I/O pin |
| 引脚 112 | I/O — User I/O pin |
| 引脚 113 | I/O — User I/O pin |
| 引脚 114 | GND — Ground |
| 引脚 115 | I/O — User I/O pin |
| 引脚 116 | I/O — User I/O pin |
| 引脚 117 | I/O — User I/O pin |
| 引脚 118 | I/O — User I/O pin |
| 引脚 119 | I/O — User I/O pin |
| 引脚 120 | I/O — User I/O pin |
| 引脚 121 | I/O — User I/O pin |
| 引脚 122 | OE2/GCLK2 — Global Output Enable 2 / Global Clock 2 |
| 引脚 123 | I/O — User I/O pin |
| 引脚 124 | I/O — User I/O pin |
| 引脚 125 | I/O — User I/O pin |
| 引脚 126 | I/O — User I/O pin |
| 引脚 127 | I/O — User I/O pin |
| 引脚 128 | I/O — User I/O pin |
| 引脚 129 | I/O — User I/O pin |
| 引脚 130 | I/O — User I/O pin |
| 引脚 131 | VCC — 5 V supply |
| 引脚 132 | I/O — User I/O pin |
| 引脚 133 | I/O — User I/O pin |
| 引脚 134 | I/O — User I/O pin |
| 引脚 135 | I/O — User I/O pin |
| 引脚 136 | I/O — User I/O pin |
| 引脚 137 | I/O — User I/O pin |
| 引脚 138 | I/O — User I/O pin |
| 引脚 139 | I/O — User I/O pin |
| 引脚 140 | I/O — User I/O pin |
| 引脚 141 | OE2/GCLK1 — Global Output Enable 2 / Global Clock 1 |
| 引脚 142 | I/O — User I/O pin |
| 引脚 143 | I/O — User I/O pin |
| 引脚 144 | I/O — User I/O pin |
| 引脚 145 | I/O — User I/O pin |
| 引脚 146 | I/O — User I/O pin |
| 引脚 147 | I/O — User I/O pin |
| 引脚 148 | I/O — User I/O pin |
| 引脚 149 | I/O — User I/O pin |
| 引脚 150 | GND — Ground |
| 引脚 151 | I/O — User I/O pin |
| 引脚 152 | I/O — User I/O pin |
| 引脚 153 | I/O — User I/O pin |
| 引脚 154 | I/O — User I/O pin |
| 引脚 155 | I/O — User I/O pin |
| 引脚 156 | I/O — User I/O pin |
| 引脚 157 | I/O — User I/O pin |
| 引脚 158 | CLR — Global Clear (active low) |
| 引脚 159 | I/O — User I/O pin |
| 引脚 160 | I/O — User I/O pin |
典型应用
EPM7256EQC160-12 适用于 6 应用s: 5V System Glue Logic, Microprocessor Address Decoding, Industrial Control State Machines, Telecom Backplane Bridging, Legacy PCI / ISA Bridge Logic, Test & Measurement Front-End Logic.
5V System Glue Logic
The EPM7256EQC160-12 is ideally suited for 5 V system glue-logic consolidation, replacing discrete 74LS/74HC TTL with a single programmable device. Its 12 ns tPD and 90.9 MHz fMAX comfortably handle 33-50 MHz bus cycles in legacy 5 V architectures such as VME, ISA, and PC/104, while the 132 I/O pins aggregate dozens of decode, latch, and mux functions onto one chip. The 256 macrocells accommodate complex address maps with multiple chip-select outputs and registered handshake logic, and the EEPROM non-volatile configuration eliminates external boot PROMs. Power dissipation stays in the 0.5-1.5 W typical range at 5 V, far below FPGAs of similar logic capacity.
推荐
Microprocessor Address Decoding
The 132-I/O EPM7256EQC160-12 consolidates full address decoding for embedded microprocessor systems, generating chip-select signals for memory and peripherals from a single device. With 16 LABs and 256 macrocells, designers can implement wide product-term decode trees for both memory and I/O maps simultaneously, plus wait-state generators and bus arbitration logic. The 12 ns propagation delay leaves comfortable margin for one-clock-state bus cycles at 33 MHz, and the JTAG in-system programmability enables last-minute board-revision fixes without swapping the part. Operating from a single 5 V rail, the part integrates cleanly with legacy 68k, x86, and PowerPC host designs.
推荐
Industrial Control State Machines
In industrial control PLC and motor-drive boards, the EPM7256EQC160-12 replaces banks of PAL/GAL devices with a single non-volatile state-machine engine. Its 256 macrocells implement complex multi-state sequencers for conveyor control, machine-tool interlocks, and process automation while the 132 I/O count interfaces directly to opto-isolated 24 V field I/O through 5 V level shifters. The MAX 7000 architecture's deterministic interconnect delay simplifies IEC 61131-3 timing analysis, and the commercial 0-70 °C range covers most factory-floor enclosures. JTAG re-programmability enables field firmware updates via boundary-scan without removing the part.
推荐
Telecom Backplane Bridging
Telecom infrastructure designs based on H.110 CT bus, MVIP, and SCSA used the EPM7256EQC160-12 to bridge time-division-multiplexed (TDM) streams between framer ICs, DSPs, and TDM switches. With 132 I/O pins and 12 ns tPD, the part handles 8 Mbps E1/T1 stream multiplexing, clock distribution, and frame-alignment logic without external glue. The 5 V supply matches legacy telecom line-card power rails, and the PQFP-160 footprint integrates into existing backplane daughter-card layouts. The non-volatile EEPROM configuration guarantees instant-on operation after power-cycle events that are routine in central-office equipment.
推荐
Legacy PCI / ISA Bridge Logic
The EPM7256EQC160-12 implements legacy PCI target devices, ISA bus arbiters, and PCI-to-ISA bridges in industrial single-board computers and instrumentation. With 256 macrocells, the part encodes full PCI configuration-space decoding plus ISA bus controllers and DMA handshake logic in one device. The 12 ns tPD meets PCI 33 MHz clock-to-output requirements with comfortable margin, and the 132 I/O count directly drives PCI bus signals plus peripheral chip-selects. JTAG boundary-scan compliance simplifies board-level interconnect testing per IEEE 1149.1.
推荐
Test & Measurement Front-End Logic
In oscilloscope, logic-analyzer, and bench-instrument front ends, the EPM7256EQC160-12 implements range-selection muxes, ADC timing generators, calibration state machines, and display-scan logic. The 132 I/O count connects directly to 8-16 channel analog muxes and LED/LCD driver arrays, while 256 macrocells encode the full measurement-cycle state machine with deterministic 12 ns step times. The EEPROM non-volatile configuration ensures instant boot into the calibration state, and the JTAG interface allows in-system firmware updates during factory calibration procedures. Single 5 V operation simplifies mixed-signal board power architecture.
推荐
推荐产品汇总
工程参考数据： EPM7256EQC160-12 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPM7256EQC160-15 | EPM7256EQC160-10 | EPM7256EQC160-12P | EPM7256EQC160-15N | EPM7256EGC192-12 |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 160-pin PQFP (28x28 mm) | 160-pin PQFP (28x28 mm) - same | 160-pin PQFP (28x28 mm) - same | 160-pin PQFP (28x28 mm) - same | 160-pin PQFP (28x28 mm) - same | 192-pin PQFP - NOT pin-compatible with 160-pin PCB |
| Macrocells | 256 | 256 | 256 | 256 | 256 | 256 |
| User I/O | 132 | 132 | 132 | 132 | 132 | 164 (more I/O due to larger package) |
| Propagation Delay tPD (max) | 12 ns | 15 ns (slower) | 10 ns (faster) | 12 ns (identical) | 15 ns (slower) | 12 ns (identical) |
| Maximum Frequency | 90.9 MHz | ~76.9 MHz | ~100 MHz | 90.9 MHz | ~76.9 MHz | 90.9 MHz |
| Supply Voltage | 4.75-5.25 V (5 V) | 4.75-5.25 V | 4.75-5.25 V | 4.75-5.25 V | 4.75-5.25 V | 4.75-5.25 V |
| Operating Temperature | 0 °C to 70 °C (Commercial) | 0 °C to 70 °C | 0 °C to 70 °C | 0 °C to 70 °C | 0 °C to 70 °C | 0 °C to 70 °C |
| Programming Interface | JTAG (IEEE 1149.1 / 1532) | JTAG | JTAG | JTAG | JTAG | JTAG |
| Approx. Price @ 1000 pcs (USD) | $17.10 | ~$15-16 (slightly cheaper) | ~$20-22 (faster, premium) | ~$17-18 (Pb-free equivalent) | ~$15-16 (Pb-free, slower) | ~$19-22 (larger package) |
关键差异点
- Best timing/cost balance in the 256-macrocell MAX 7000 family （对比 EPM7256EQC160-10)
- Drop-in pin-compatible upgrade path within the same PQFP-160 footprint （对比 EPM7256AQC208-7)
- Faster propagation delay available in the same footprint （对比 EPM7256EQC160-15)
设计说明
Estimated: At 5 V VCC, ICC quiescent is approximately 100-300 mA (depends on logic utilization and toggle rate). Bulk-decouple each VCC pin (33, 69, 97, 131) with a 0.1 µF ceramic placed within 5 mm of the pin, and add one bulk 10-47 µF tantalum or aluminum-polymer capacitor near the package. The MAX 7000 family does not require external configuration memory, but in-rush current during EEPROM programming can briefly exceed 200 mA per VCC pin - size your regulator accordingly.
The PQFP-160 package has 0.65 mm pitch gull-wing leads with a 28 × 28 mm body. Use a 4-layer PCB with one solid ground plane under the part and one 5 V power plane on an adjacent layer; route all 132 I/O signals on the outer layers with matched impedance for clock and JTAG signals. Leave at least 3 mm clearance around the package for inspection and rework. JTAG signals (TDI, TMS, TCK, TDO) must be length-matched within 25 mm to avoid boundary-scan shift-register glitches.
Do not confuse the EPM7256EQC160-12 (5 V commercial, PQFP-160) with the EPM7256AQC208-7 (also 5 V commercial but PQFP-208 with 7.5 ns tPD) - the pin counts and footprints differ. Do not assume any modern Quartus version supports MAX 7000 - use Quartus 13.0sp1 or MAX+PLUS II 10.2 as your design entry. If migrating legacy designs, verify the JTAG chain order against the BSDL file before production programming.
合规信息
RoHS compliance depends on date code - check manufacturer marking for Pb-free suffix (P or N suffix). Not AEC-Q100 qualified; the commercial 0-70 °C grade is not intended for automotive.
