EPM7256EQC160-12 - MAX 7000 CPLD, 256 Macrocells, 12ns, PQFP-160
MPN: EPM7256EQC160-12 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.2 | $252.00 |
| 100 | $21.8 | $2,180.00 |
| 500 | $19.4 | $9,700.00 |
| 1,000 | $17.1 | $17,100.00 |
Drop-in alternatives for EPM7256EQC160-12 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7256EQC160-15
β Drop-Inπ Reference alternative (not in catalog)
EPM7256EQC160-10
β Drop-Inπ Reference alternative (not in catalog)
EPM7256EQC160-12P
β Drop-Inπ Reference alternative (not in catalog)
EPM7256EQC160-15N
β Drop-Inπ Reference alternative (not in catalog)
EPM7256EGC192-12
β Drop-Inβ In Stock
$17.85 / Unit
View Datasheet βEPM7256EQC160-12 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000 |
| Programmable Type | EE PLD (CPLD, in-system programmable EEPROM) |
| Number of Macrocells | 256 |
| Number of Logic Blocks / LABs | 16 |
| Number of Gates | 5,000 usable gates |
| Number of I/O Pins | 132 |
| Propagation Delay tPD (max) | 12 ns |
| Maximum Operating Frequency | 90.9 MHz |
| Supply Voltage VCCINT | 4.75 V to 5.25 V |
| I/O Standard | 5 V TTL, 3.3 V compatible |
| Operating Temperature | 0 Β°C to 70 Β°C (Commercial) |
| Package / Case | 160-pin PQFP (28 Γ 28 mm) |
| Mounting Type | Surface Mount |
| Process Technology | CMOS EEPROM |
| Programming Interface | JTAG (IEEE 1532 / IEEE 1149.1) |
| RoHS Status | Compliant (lead-free PQFP) |
| Lifecycle Status | Obsolete |
EPM7256EQC160-12 Pin Configuration
| Pin 1 | I/O β User I/O pin (function depends on user design) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | I/O β User I/O pin |
| Pin 6 | I/O β User I/O pin |
| Pin 7 | GND β Ground |
| Pin 8 | I/O β User I/O pin |
| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | I/O β User I/O pin |
| Pin 12 | I/O β User I/O pin |
| Pin 13 | I/O β User I/O pin |
| Pin 14 | I/O β User I/O pin |
| Pin 15 | TDI β JTAG Test Data In (IEEE 1149.1) |
| Pin 16 | I/O β User I/O pin |
| Pin 17 | I/O β User I/O pin |
| Pin 18 | I/O β User I/O pin |
| Pin 19 | I/O β User I/O pin |
| Pin 20 | I/O β User I/O pin |
| Pin 21 | I/O β User I/O pin |
| Pin 22 | I/O β User I/O pin |
| Pin 23 | I/O β User I/O pin |
| Pin 24 | I/O β User I/O pin |
| Pin 25 | GND β Ground |
| Pin 26 | I/O β User I/O pin |
| Pin 27 | I/O β User I/O pin |
| Pin 28 | I/O β User I/O pin |
| Pin 29 | I/O β User I/O pin |
| Pin 30 | I/O β User I/O pin |
| Pin 31 | I/O β User I/O pin |
| Pin 32 | I/O β User I/O pin |
| Pin 33 | VCC β 5 V supply |
| Pin 34 | I/O β User I/O pin |
| Pin 35 | I/O β User I/O pin |
| Pin 36 | I/O β User I/O pin |
| Pin 37 | I/O β User I/O pin |
| Pin 38 | I/O β User I/O pin |
| Pin 39 | I/O β User I/O pin |
| Pin 40 | I/O β User I/O pin |
| Pin 41 | TMS β JTAG Test Mode Select |
| Pin 42 | I/O β User I/O pin |
| Pin 43 | I/O β User I/O pin |
| Pin 44 | I/O β User I/O pin |
| Pin 45 | I/O β User I/O pin |
| Pin 46 | I/O β User I/O pin |
| Pin 47 | I/O β User I/O pin |
| Pin 48 | I/O β User I/O pin |
| Pin 49 | I/O β User I/O pin |
| Pin 50 | I/O β User I/O pin |
| Pin 51 | GND β Ground |
| Pin 52 | I/O β User I/O pin |
| Pin 53 | I/O β User I/O pin |
| Pin 54 | I/O β User I/O pin |
| Pin 55 | I/O β User I/O pin |
| Pin 56 | I/O β User I/O pin |
| Pin 57 | I/O β User I/O pin |
| Pin 58 | I/O β User I/O pin |
| Pin 59 | TCK β JTAG Test Clock |
| Pin 60 | I/O β User I/O pin |
| Pin 61 | I/O β User I/O pin |
| Pin 62 | I/O β User I/O pin |
| Pin 63 | I/O β User I/O pin |
| Pin 64 | I/O β User I/O pin |
| Pin 65 | I/O β User I/O pin |
| Pin 66 | I/O β User I/O pin |
| Pin 67 | I/O β User I/O pin |
| Pin 68 | I/O β User I/O pin |
| Pin 69 | VCC β 5 V supply |
| Pin 70 | I/O β User I/O pin |
| Pin 71 | I/O β User I/O pin |
| Pin 72 | I/O β User I/O pin |
| Pin 73 | I/O β User I/O pin |
| Pin 74 | I/O β User I/O pin |
| Pin 75 | I/O β User I/O pin |
| Pin 76 | I/O β User I/O pin |
| Pin 77 | TDO β JTAG Test Data Out |
| Pin 78 | I/O β User I/O pin |
| Pin 79 | I/O β User I/O pin |
| Pin 80 | I/O β User I/O pin |
| Pin 81 | I/O β User I/O pin |
| Pin 82 | I/O β User I/O pin |
| Pin 83 | I/O β User I/O pin |
| Pin 84 | I/O β User I/O pin |
| Pin 85 | I/O β User I/O pin |
| Pin 86 | GND β Ground |
| Pin 87 | I/O β User I/O pin |
| Pin 88 | I/O β User I/O pin |
| Pin 89 | I/O β User I/O pin |
| Pin 90 | I/O β User I/O pin |
| Pin 91 | I/O β User I/O pin |
| Pin 92 | I/O β User I/O pin |
| Pin 93 | I/O β User I/O pin |
| Pin 94 | I/O β User I/O pin |
| Pin 95 | I/O β User I/O pin |
| Pin 96 | I/O β User I/O pin |
| Pin 97 | VCC β 5 V supply |
| Pin 98 | I/O β User I/O pin |
| Pin 99 | I/O β User I/O pin |
| Pin 100 | I/O β User I/O pin |
| Pin 101 | I/O β User I/O pin |
| Pin 102 | I/O β User I/O pin |
| Pin 103 | I/O β User I/O pin |
| Pin 104 | I/O β User I/O pin |
| Pin 105 | OE1 β Global Output Enable 1 (active low) |
| Pin 106 | I/O β User I/O pin |
| Pin 107 | I/O β User I/O pin |
| Pin 108 | I/O β User I/O pin |
| Pin 109 | I/O β User I/O pin |
| Pin 110 | I/O β User I/O pin |
| Pin 111 | I/O β User I/O pin |
| Pin 112 | I/O β User I/O pin |
| Pin 113 | I/O β User I/O pin |
| Pin 114 | GND β Ground |
| Pin 115 | I/O β User I/O pin |
| Pin 116 | I/O β User I/O pin |
| Pin 117 | I/O β User I/O pin |
| Pin 118 | I/O β User I/O pin |
| Pin 119 | I/O β User I/O pin |
| Pin 120 | I/O β User I/O pin |
| Pin 121 | I/O β User I/O pin |
| Pin 122 | OE2/GCLK2 β Global Output Enable 2 / Global Clock 2 |
| Pin 123 | I/O β User I/O pin |
| Pin 124 | I/O β User I/O pin |
| Pin 125 | I/O β User I/O pin |
| Pin 126 | I/O β User I/O pin |
| Pin 127 | I/O β User I/O pin |
| Pin 128 | I/O β User I/O pin |
| Pin 129 | I/O β User I/O pin |
| Pin 130 | I/O β User I/O pin |
| Pin 131 | VCC β 5 V supply |
| Pin 132 | I/O β User I/O pin |
| Pin 133 | I/O β User I/O pin |
| Pin 134 | I/O β User I/O pin |
| Pin 135 | I/O β User I/O pin |
| Pin 136 | I/O β User I/O pin |
| Pin 137 | I/O β User I/O pin |
| Pin 138 | I/O β User I/O pin |
| Pin 139 | I/O β User I/O pin |
| Pin 140 | I/O β User I/O pin |
| Pin 141 | OE2/GCLK1 β Global Output Enable 2 / Global Clock 1 |
| Pin 142 | I/O β User I/O pin |
| Pin 143 | I/O β User I/O pin |
| Pin 144 | I/O β User I/O pin |
| Pin 145 | I/O β User I/O pin |
| Pin 146 | I/O β User I/O pin |
| Pin 147 | I/O β User I/O pin |
| Pin 148 | I/O β User I/O pin |
| Pin 149 | I/O β User I/O pin |
| Pin 150 | GND β Ground |
| Pin 151 | I/O β User I/O pin |
| Pin 152 | I/O β User I/O pin |
| Pin 153 | I/O β User I/O pin |
| Pin 154 | I/O β User I/O pin |
| Pin 155 | I/O β User I/O pin |
| Pin 156 | I/O β User I/O pin |
| Pin 157 | I/O β User I/O pin |
| Pin 158 | CLR β Global Clear (active low) |
| Pin 159 | I/O β User I/O pin |
| Pin 160 | I/O β User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7256EQC160-12 is suitable for 6 applications: 5V System Glue Logic, Microprocessor Address Decoding, Industrial Control State Machines, Telecom Backplane Bridging, Legacy PCI / ISA Bridge Logic, Test & Measurement Front-End Logic.
5V System Glue Logic
The EPM7256EQC160-12 is ideally suited for 5 V system glue-logic consolidation, replacing discrete 74LS/74HC TTL with a single programmable device. Its 12 ns tPD and 90.9 MHz fMAX comfortably handle 33-50 MHz bus cycles in legacy 5 V architectures such as VME, ISA, and PC/104, while the 132 I/O pins aggregate dozens of decode, latch, and mux functions onto one chip. The 256 macrocells accommodate complex address maps with multiple chip-select outputs and registered handshake logic, and the EEPROM non-volatile configuration eliminates external boot PROMs. Power dissipation stays in the 0.5-1.5 W typical range at 5 V, far below FPGAs of similar logic capacity.
Recommended
Microprocessor Address Decoding
The 132-I/O EPM7256EQC160-12 consolidates full address decoding for embedded microprocessor systems, generating chip-select signals for memory and peripherals from a single device. With 16 LABs and 256 macrocells, designers can implement wide product-term decode trees for both memory and I/O maps simultaneously, plus wait-state generators and bus arbitration logic. The 12 ns propagation delay leaves comfortable margin for one-clock-state bus cycles at 33 MHz, and the JTAG in-system programmability enables last-minute board-revision fixes without swapping the part. Operating from a single 5 V rail, the part integrates cleanly with legacy 68k, x86, and PowerPC host designs.
Recommended
Industrial Control State Machines
In industrial control PLC and motor-drive boards, the EPM7256EQC160-12 replaces banks of PAL/GAL devices with a single non-volatile state-machine engine. Its 256 macrocells implement complex multi-state sequencers for conveyor control, machine-tool interlocks, and process automation while the 132 I/O count interfaces directly to opto-isolated 24 V field I/O through 5 V level shifters. The MAX 7000 architecture's deterministic interconnect delay simplifies IEC 61131-3 timing analysis, and the commercial 0-70 Β°C range covers most factory-floor enclosures. JTAG re-programmability enables field firmware updates via boundary-scan without removing the part.
Recommended
Telecom Backplane Bridging
Telecom infrastructure designs based on H.110 CT bus, MVIP, and SCSA used the EPM7256EQC160-12 to bridge time-division-multiplexed (TDM) streams between framer ICs, DSPs, and TDM switches. With 132 I/O pins and 12 ns tPD, the part handles 8 Mbps E1/T1 stream multiplexing, clock distribution, and frame-alignment logic without external glue. The 5 V supply matches legacy telecom line-card power rails, and the PQFP-160 footprint integrates into existing backplane daughter-card layouts. The non-volatile EEPROM configuration guarantees instant-on operation after power-cycle events that are routine in central-office equipment.
Recommended
Legacy PCI / ISA Bridge Logic
The EPM7256EQC160-12 implements legacy PCI target devices, ISA bus arbiters, and PCI-to-ISA bridges in industrial single-board computers and instrumentation. With 256 macrocells, the part encodes full PCI configuration-space decoding plus ISA bus controllers and DMA handshake logic in one device. The 12 ns tPD meets PCI 33 MHz clock-to-output requirements with comfortable margin, and the 132 I/O count directly drives PCI bus signals plus peripheral chip-selects. JTAG boundary-scan compliance simplifies board-level interconnect testing per IEEE 1149.1.
Recommended
Test & Measurement Front-End Logic
In oscilloscope, logic-analyzer, and bench-instrument front ends, the EPM7256EQC160-12 implements range-selection muxes, ADC timing generators, calibration state machines, and display-scan logic. The 132 I/O count connects directly to 8-16 channel analog muxes and LED/LCD driver arrays, while 256 macrocells encode the full measurement-cycle state machine with deterministic 12 ns step times. The EEPROM non-volatile configuration ensures instant boot into the calibration state, and the JTAG interface allows in-system firmware updates during factory calibration procedures. Single 5 V operation simplifies mixed-signal board power architecture.
Recommended
Recommended Products Summary
Engineering reference data for EPM7256EQC160-12 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7256EQC160-15 | EPM7256EQC160-10 | EPM7256EQC160-12P | EPM7256EQC160-15N | EPM7256EGC192-12 |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 160-pin PQFP (28x28 mm) | 160-pin PQFP (28x28 mm) - same | 160-pin PQFP (28x28 mm) - same | 160-pin PQFP (28x28 mm) - same | 160-pin PQFP (28x28 mm) - same | 192-pin PQFP - NOT pin-compatible with 160-pin PCB |
| Macrocells | 256 | 256 | 256 | 256 | 256 | 256 |
| User I/O | 132 | 132 | 132 | 132 | 132 | 164 (more I/O due to larger package) |
| Propagation Delay tPD (max) | 12 ns | 15 ns (slower) | 10 ns (faster) | 12 ns (identical) | 15 ns (slower) | 12 ns (identical) |
| Maximum Frequency | 90.9 MHz | ~76.9 MHz | ~100 MHz | 90.9 MHz | ~76.9 MHz | 90.9 MHz |
| Supply Voltage | 4.75-5.25 V (5 V) | 4.75-5.25 V | 4.75-5.25 V | 4.75-5.25 V | 4.75-5.25 V | 4.75-5.25 V |
| Operating Temperature | 0 Β°C to 70 Β°C (Commercial) | 0 Β°C to 70 Β°C | 0 Β°C to 70 Β°C | 0 Β°C to 70 Β°C | 0 Β°C to 70 Β°C | 0 Β°C to 70 Β°C |
| Programming Interface | JTAG (IEEE 1149.1 / 1532) | JTAG | JTAG | JTAG | JTAG | JTAG |
| Approx. Price @ 1000 pcs (USD) | $17.10 | ~$15-16 (slightly cheaper) | ~$20-22 (faster, premium) | ~$17-18 (Pb-free equivalent) | ~$15-16 (Pb-free, slower) | ~$19-22 (larger package) |
Key Differentiators
- Best timing/cost balance in the 256-macrocell MAX 7000 family (vs EPM7256EQC160-10)
- Drop-in pin-compatible upgrade path within the same PQFP-160 footprint (vs EPM7256AQC208-7)
- Faster propagation delay available in the same footprint (vs EPM7256EQC160-15)
Design Notes
Estimated: At 5 V VCC, ICC quiescent is approximately 100-300 mA (depends on logic utilization and toggle rate). Bulk-decouple each VCC pin (33, 69, 97, 131) with a 0.1 Β΅F ceramic placed within 5 mm of the pin, and add one bulk 10-47 Β΅F tantalum or aluminum-polymer capacitor near the package. The MAX 7000 family does not require external configuration memory, but in-rush current during EEPROM programming can briefly exceed 200 mA per VCC pin - size your regulator accordingly.
The PQFP-160 package has 0.65 mm pitch gull-wing leads with a 28 Γ 28 mm body. Use a 4-layer PCB with one solid ground plane under the part and one 5 V power plane on an adjacent layer; route all 132 I/O signals on the outer layers with matched impedance for clock and JTAG signals. Leave at least 3 mm clearance around the package for inspection and rework. JTAG signals (TDI, TMS, TCK, TDO) must be length-matched within 25 mm to avoid boundary-scan shift-register glitches.
Do not confuse the EPM7256EQC160-12 (5 V commercial, PQFP-160) with the EPM7256AQC208-7 (also 5 V commercial but PQFP-208 with 7.5 ns tPD) - the pin counts and footprints differ. Do not assume any modern Quartus version supports MAX 7000 - use Quartus 13.0sp1 or MAX+PLUS II 10.2 as your design entry. If migrating legacy designs, verify the JTAG chain order against the BSDL file before production programming.
Compliance Information
RoHS compliance depends on date code - check manufacturer marking for Pb-free suffix (P or N suffix). Not AEC-Q100 qualified; the commercial 0-70 Β°C grade is not intended for automotive.
