LPC1345FBD48,151 - 32KB Cortex-M3 MCU 72MHz LQFP-48 | NXP
料号： LPC1345FBD48,151 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $3.62 | $3.62 |
| 10 | $3.35 | $33.50 |
| 100 | $3.05 | $305.00 |
| 500 | $2.85 | $1,425.00 |
| 1,000 | $2.62 | $2,620.00 |
LPC1345FBD48,151 概述
An Arm Cortex-M3 microcontroller is a class of embedded processor built on the Armv7-M architecture with a 3-stage pipeline, Harvard architecture with separate instruction and data buses, and an integrated nested vectored interrupt controller (NVIC). Within the embedded system hierarchy, an MCU combines a CPU core, flash memory, SRAM, and peripherals such as USB, UART, SPI, and I2C into a single chip, making it a complete system-on-chip for embedded applications. The LPC13xx family occupies the entry-level tier of NXP's LPC microcontroller portfolio, below the LPC15xx and LPC40xxx families.
Key features of the LPC1345FBD48 include the enhanced debug capability of the Cortex-M3 core, low power consumption, and a high level of peripheral integration on a single die. According to NXP's product page, the Cortex-M3 core offers system enhancements such as enhanced debug features and a higher level of support block integration, plus an internal prefetch unit supporting speculative branching.
The Harvard architecture with separate local instruction and data buses plus a dedicated peripheral bus sustains near single-cycle throughput at 72 MHz, while the prefetch unit keeps the pipeline fed from zero-wait-state SRAM. The integrated USB device controller, boot ROM with USB in-system programming, and serial interfaces (UART, SPI, I2C) reduce bill-of-materials count for USB-connected designs.
Typical applications include USB HID device firmware, industrial control nodes, consumer appliance interfaces, and general-purpose embedded control where a 32-bit upgrade path from 8-bit MCUs is desired. The 7x7 mm LQFP-48 footprint suits compact, hand-solderable and reflow-compatible two-layer boards.
Design consideration: budget flash and SRAM carefully - the 32 KB flash / 8-12 KB SRAM combination of the LPC1345 is adequate for HID-class USB applications but tight for USB composite classes with RTOS; step up to the pin-compatible LPC1347 (64 KB) if headroom is needed.
This page synthesizes distributor pricing, pin-compatible same-family alternatives, pinout guidance, and practical design notes not consolidated in the manufacturer datasheet.
直接替换替代料： LPC1345FBD48,151 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： LPC1345FBD48,151 （相同外形与封装尺寸） ——差异在于 Package, Flash Memory, Package Shape, SRAM, USB.
快速对比工具——选择替代料号进行并排对比：
LPC1346FBD48,151
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
LPC1347FBD48,151
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
LPC1342FBD48,151
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$1.54 / 个
查看数据手册 →LPC1343FBD48,151
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$4.62 / 个
查看数据手册 →LPC1345FBD48,251
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
LPC1345FBD48,151 最大额定值与电气特性
| Core | ARM Cortex-M3 |
| Core Architecture | 32-bit Harvard, 3-stage pipeline |
| Maximum CPU Frequency | 72 MHz |
| Flash Memory | 32 KB |
| USB | USB 2.0 full-speed device controller |
| 封装 | 48-LQFP (7 x 7 mm) |
| 安装类型 | Surface Mount |
| Temperature Grade | Industrial |
| Terminal Form | Gull Wing |
| Package Shape | Square, LFQFP |
| Peripherals | UART, SPI, I2C, ADC, USB |
| RoHS 状态 | Compliant |
LPC1345FBD48,151 引脚配置
| 引脚 1 | P0_16 — GPIO0_16 with multiplexed analog/timer functions (verify against datasheet pin function table) |
| 引脚 2 | P0_13 — GPIO0_13 multiplexed I/O |
| 引脚 3 | P0_12 — GPIO0_12 multiplexed I/O |
| 引脚 4 | P0_11 — GPIO0_11 multiplexed I/O |
| 引脚 5 | P0_10 — GPIO0_10 multiplexed I/O |
| 引脚 6 | VSS — Ground |
| 引脚 7 | VDD — 3.3 V power supply |
| 引脚 8 | P0_9 — GPIO0_9 multiplexed I/O (UART RXD location) |
| 引脚 9 | P0_8 — GPIO0_8 multiplexed I/O (UART TXD location) |
| 引脚 10 | P0_7 — GPIO0_7 multiplexed I/O |
| 引脚 11 | P0_6 — GPIO0_6 multiplexed I/O |
| 引脚 12 | P0_5 — GPIO0_5 multiplexed I/O |
| 引脚 13 | P0_4 — GPIO0_4 multiplexed I/O |
| 引脚 14 | P0_3 — GPIO0_3 multiplexed I/O (USB-related pad) |
| 引脚 15 | P0_2 — GPIO0_2 multiplexed I/O (USB-related pad) |
| 引脚 16 | P0_1 — GPIO0_1 multiplexed I/O (USB D- on fixed pad) |
| 引脚 17 | P0_0 — GPIO0_0 multiplexed I/O (USB D+ on fixed pad) |
| 引脚 18 | RESET — External reset input |
| 引脚 19 | P0_23 — GPIO0_23 multiplexed I/O |
| 引脚 20 | P0_22 — GPIO0_22 multiplexed I/O |
| 引脚 21 | P0_21 — GPIO0_21 multiplexed I/O |
| 引脚 22 | P0_20 — GPIO0_20 multiplexed I/O |
| 引脚 23 | P0_19 — GPIO0_19 multiplexed I/O |
| 引脚 24 | P0_18 — GPIO0_18 multiplexed I/O |
| 引脚 25 | P0_17 — GPIO0_17 multiplexed I/O |
| 引脚 26 | VSS — Ground |
| 引脚 27 | VDD — 3.3 V power supply |
| 引脚 28 | P1_15 — GPIO1_15 multiplexed I/O |
| 引脚 29 | P1_14 — GPIO1_14 multiplexed I/O |
| 引脚 30 | P1_13 — GPIO1_13 multiplexed I/O |
| 引脚 31 | P1_12 — GPIO1_12 multiplexed I/O |
| 引脚 32 | P1_11 — GPIO1_11 multiplexed I/O |
| 引脚 33 | P1_10 — GPIO1_10 multiplexed I/O |
| 引脚 34 | P1_9 — GPIO1_9 multiplexed I/O |
| 引脚 35 | P1_8 — GPIO1_8 multiplexed I/O |
| 引脚 36 | P1_7 — GPIO1_7 multiplexed I/O |
| 引脚 37 | P1_6 — GPIO1_6 multiplexed I/O |
| 引脚 38 | P1_5 — GPIO1_5 multiplexed I/O |
| 引脚 39 | P1_4 — GPIO1_4 multiplexed I/O |
| 引脚 40 | P1_3 — GPIO1_3 multiplexed I/O |
| 引脚 41 | P1_2 — GPIO1_2 multiplexed I/O |
| 引脚 42 | P1_1 — GPIO1_1 multiplexed I/O |
| 引脚 43 | P1_0 — GPIO1_0 multiplexed I/O |
| 引脚 44 | VDD — 3.3 V power supply |
| 引脚 45 | VSS — Ground |
| 引脚 46 | XTALIN — Crystal oscillator input |
| 引脚 47 | XTALOUT — Crystal oscillator output |
| 引脚 48 | VDDA — Analog power supply / reference |
典型应用
LPC1345FBD48,151 适用于 6 应用s: USB HID Devices, Industrial Control Nodes, Consumer Appliance Interfaces, Embedded USB Bridges and Dongles, Battery-Powered Portable Devices, 32-bit Migration from 8-bit MCUs.
USB HID Devices
The LPC1345FBD48,151 is a natural fit for USB HID devices such as keyboards, game controllers, and sensor dongles because it integrates a USB 2.0 full-speed device controller and NXP boot ROM with USB in-system programming. The 72 MHz Cortex-M3 core with a 3-stage pipeline processes interrupt-endpoint traffic with minimal latency, while 32 KB flash comfortably holds HID-class descriptors, report handlers, and application logic without an RTOS. Placed on a 7x7 mm LQFP-48 footprint with USB D+/D- on fixed pads, the design needs only 22-ohm series termination resistors and a 1.5 kohm pull-up on D-, which NXP documents in its USB application notes. This yields a two-chip-plus-passives BOM for a fully compliant full-speed HID product.
推荐
Industrial Control Nodes
In industrial control nodes such as sensor hubs, relay controllers, and PLC I/O modules, the LPC1345FBD48,151 provides the required industrial temperature grade, 3.3 V operation, and a rich peripheral mix of UART, SPI, I2C, and ADC on one chip. The 72 MHz Cortex-M3 delivers deterministic interrupt response via the NVIC for time-critical polling and control loops, and its low power consumption suits always-on monitoring nodes. The 32 KB flash is sufficient for Modbus-RTU slaves and protocol bridges, while the same footprint accommodates the pin-compatible LPC1347 with 64 KB flash if firmware grows to include fieldbus stacks. Gull-wing LQFP-48 terminals withstand standard industrial reflow and wave-solder processes, and NXP's switch-matrix documentation simplifies pin function planning.
推荐
Consumer Appliance Interfaces
Consumer appliance user interfaces - oven panels, fan controllers, and small home devices - benefit from the LPC1345FBD48,151's combination of low cost (about $3.62 unit price as of 2026-10-10), low power consumption, and adequate performance. The ADC digitizes potentiometers and NTC temperature sensors, I2C drives segment-LCD or OLED controllers, and GPIO handles buttons and buzzers directly. Entry-level Cortex-M3 code density means touch-debounce, menu logic, and LED multiplexing all fit in 32 KB flash with margin. The 48-LQFP 7x7 mm package is large enough for hand-solderable rework in low-volume appliance production yet compatible with high-volume reflow lines, and the family's pin-compatible flash upgrade path protects the PCB layout across product tiers.
推荐
Embedded USB Bridges and Dongles
USB-to-UART, USB-to-SPI, and USB-to-I2C bridge dongles leverage the LPC1345FBD48,151's full-speed USB device controller plus its native serial peripherals, eliminating an external bridge chip. Data arriving over the 12 Mbps USB link is buffered in SRAM and forwarded by hardware UART or SPI under a lightweight CDC-class firmware stack that fits within 32 KB flash. Because the Cortex-M3 core runs at 72 MHz with zero-wait-state SRAM, sustained bridge throughput remains bounded by USB full-speed bandwidth rather than CPU load. NXP's boot ROM USB ISP support also lets end users update dongle firmware by plugging into a host - a strong field-upgradeability argument that discrete bridge ICs cannot match without extra circuitry.
推荐
Battery-Powered Portable Devices
Portable and battery-operated designs such as measurement loggers and handheld instruments exploit the LPC13xx family's low power consumption and multiple reduced-power modes documented in the NXP datasheet. The Cortex-M3 supports sleep and deep-sleep states controlled through the NVIC and power-management unit, letting firmware duty-cycle the 72 MHz core between acquisition bursts. The integrated ADC reads sensor fronts directly, SPI talks to flash cards or RF modules, and the compact 7x7 mm LQFP-48 fits slim enclosures. With 32 KB flash, a data-logging application storing calibration tables and a CDC upload path remains within budget; designers needing more storage stay on the same PCB footprint and drop in the pin-compatible LPC1347.
推荐
32-bit Migration from 8-bit MCUs
Designers upgrading from 8-bit MCUs (PIC16/18, 8051) choose the LPC1345FBD48,151 as a low-risk first 32-bit step: it costs under $4 as of 2026-10-10, runs from the same 3.3 V rails, and its gull-wing LQFP-48 is hand-solderable like legacy TQFP 8-bit parts. The Cortex-M3 architecture with Thumb-2 instructions gives substantially higher code density than 8-bit cores, so existing control logic ports quickly, while the 72 MHz clock and 32-bit ALU handle arithmetic that strained 8-bit parts, such as PID loops and CRC computation. NXP's free MCUXpresso toolchain and CMSIS ecosystem lower the software barrier, and the family's flash-size ladder (16/32/48/64 KB in one package) provides a scaling path without PCB changes.
推荐
推荐产品汇总
工程参考数据： LPC1345FBD48,151 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | LPC1346FBD48,151 | LPC1347FBD48,151 | LPC1342FBD48,151 | LPC1343FBD48,151 |
|---|---|---|---|---|---|
| Package | 48-LQFP (7x7 mm) | 48-LQFP (7x7 mm) - same | 48-LQFP (7x7 mm) - same | 48-LQFP (7x7 mm) - same | 48-LQFP (7x7 mm) - same |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Core / Max Frequency | Cortex-M3 / 72 MHz | Cortex-M3 / 72 MHz | Cortex-M3 / 72 MHz | Cortex-M3 / 72 MHz | Cortex-M3 / 72 MHz |
| Flash Memory | 32 KB | 48 KB | 64 KB | 16 KB | 32 KB |
| USB Device Controller | USB 2.0 full-speed device | USB 2.0 full-speed device | USB 2.0 full-speed device | USB 2.0 full-speed device | USB 2.0 full-speed device |
| Flash Upgrade Path | Baseline (32 KB) | +50% flash | +100% flash | -50% flash (cost down) | same flash, earlier generation |
| Family Generation | LPC1315/45/46/47 subfamily | LPC1315/45/46/47 subfamily | LPC1315/45/46/47 subfamily | LPC1315/45/46/47 subfamily | Original LPC13xx generation |
关键差异点
- Balanced 32 KB flash for entry-level USB designs （对比 LPC1347FBD48,151)
- USB ISP boot ROM for field firmware updates （对比 LPC1343FBD48,151)
- Same-footprint flash scaling ladder （对比 LPC1342FBD48,151)
设计说明
Decouple each VDD/VDDA pin pair with 100 nF ceramic capacitors placed within 2 mm of the pin, plus one bulk 4.7-10 uF capacitor near the LQFP-48. The VDDA analog supply (pin 48) benefits from an RC filter (e.g., 10 ohm series resistor + 1 uF) to isolate ADC and internal PLL noise from the digital rail. Keep the ground return path under the USB D+/D- traces intact - avoid crossing plane splits on the 7x7 mm footprint's breakout region.
Route USB D+ and D- as a 90-ohm differential pair with length matching better than 1 mm and place 22-ohm series resistors close to the MCU pins, per NXP's LPC13xx USB hardware design guidance. Full-speed USB edges are fast enough that stubs longer than 10 mm cause reflections; keep the connector within about 10 cm of the device. If the crystal (pins 46/47) sits more than 10 mm from the MCU, add ground guard traces around XTALIN/XTALOUT to avoid stray coupling that shifts oscillator startup margin.
Budget flash conservatively: 32 KB is ample for HID-class USB but tight once an RTOS, file system, or composite USB classes are added - reserve the pin-compatible LPC1347FBD48 (64 KB) as a same-footprint fallback before tape-out. Many LQFP-48 pads are multiplexed between USB, ADC, and digital functions, so verify every pin assignment in the datasheet switch-matrix table before routing; two planned functions may share one pad. Also confirm reset and ISP entry (PIO0_1-type pads) are accessible for field programming.
合规信息
RoHS compliance per NXP standard product suffix ,151. AEC-Q100 qualification not claimed for the LPC13xx entry-level family; verify environmental declarations on nxp.com for REACH/halogen specifics.
