LPC5526JBD64E - Cortex-M33 150MHz 256KB MCU | NXP
料号： LPC5526JBD64E ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $4.3 | $4.30 |
| 10 | $3.92 | $39.20 |
| 100 | $3.55 | $355.00 |
| 500 | $3.21 | $1,605.00 |
| 1,000 | $2.95 | $2,950.00 |
LPC5526JBD64E 概述
A microcontroller (MCU) is a single-chip embedded computer integrating a processor core, memory, and peripherals on one die. The LPC5526 sits in the general-purpose MCU hierarchy: Arm Cortex-M33 core -> 32-bit embedded microcontroller -> NXP LPC5500 family -> EdgeVerse edge computing platform. Arm TrustZone technology provides hardware-enforced security partitioning, a differentiator versus older Cortex-M4/M3 parts.
Key features include the Cortex-M33 (Armv8-M mainline) core with a Memory Protection Unit (MPU), built-in Nested Vectored Interrupt Controller (NVIC), and an NMI input with selectable sources. The device leverages a cost-effective 40-nm NVM process technology. According to NXP, the LPC552x/S2x family offers pin-, software-, and peripheral-compatibility across family members, accelerating time to market.
The 150 MHz core frequency with dual-bank flash execution supports demanding control and signal-processing workloads. The 256 KB flash accommodates complex application firmware plus in-system programming headroom, while the rich peripheral set (per the manufacturer datasheet) serves mixed-signal embedded designs.
Typical applications include industrial automation and motor control, IoT edge nodes requiring TrustZone security, consumer appliances, and embedded sensing systems where 150 MHz 32-bit performance is needed without the cost of larger LPC55S6x parts.
Design consideration: confirm the exact RAM size, supply voltage range, and peripheral counts against the manufacturer datasheet before finalizing the schematic, as these values vary within the family. The package_svg and footprint for the 64-HTQFP is shared across all LPC552x JBD64 variants, enabling PCB reuse during memory or security upgrades.
This page synthesizes distributor pricing, drop-in same-family alternatives, and practical design notes not found in the manufacturer datasheet.
直接替换替代料： LPC5526JBD64E ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： LPC5526JBD64E （相同外形与封装尺寸） ——差异在于 Interrupt Controller, Package, Flash Memory, Core Processor, Process Technology.
快速对比工具——选择替代料号进行并排对比：
LPC5526JBD64K
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$3.52 / 个
查看数据手册 →LPC5528JBD64E
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
LPC55S26JBD64E
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$3.02 / 个
查看数据手册 →LPC55S28JBD64E
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$3.44 / 个
查看数据手册 →LPC5516JBD64E
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
LPC5526JBD64
✅ 直接替换📋 参考替代料（不在目录中）
LPC5526JBD64E 最大额定值与电气特性
| Core Processor | ARM Cortex-M33 (r0p3) |
| Core Size | 32-Bit |
| 最大时钟频率 | 150 MHz |
| Flash Memory | 256KB (256K x 8) |
| Security Feature | ARM TrustZone |
| Memory Protection Unit | Yes (MPU) |
| Interrupt Controller | NVIC (built-in) |
| NMI Input | Yes, with selection of sources |
| Process Technology | 40 nm NVM |
| 封装 | 64-HTQFP (10x10 mm) |
| 安装类型 | Surface Mount |
| 湿敏等级（MSL） | 3 |
| Peak Reflow Temperature | 260 C |
| Max Time At Peak Reflow | 30 s |
| Terminal Finish | Tin (JESD-609 code e3) |
| RoHS 状态 | Compliant |
| 生命周期状态 | Active |
LPC5526JBD64E 引脚配置
| 引脚 1 | PIO1_0 / ADC0_9 — GPIO port 1 pin 0 / ADC0 channel 9 (per datasheet pin config chapter) |
| 引脚 2 | PIO1_1 / ADC0_8 — GPIO port 1 pin 1 / ADC0 channel 8 |
| 引脚 3 | PIO1_2 — GPIO port 1 pin 2 with alternate functions |
| 引脚 4 | PIO1_3 — GPIO port 1 pin 3 with alternate functions |
| 引脚 5 | PIO1_4 — GPIO port 1 pin 4 with alternate functions |
| 引脚 6 | PIO1_5 — GPIO port 1 pin 5 with alternate functions |
| 引脚 7 | PIO1_6 — GPIO port 1 pin 6 with alternate functions |
| 引脚 8 | PIO1_7 — GPIO port 1 pin 7 with alternate functions |
| 引脚 9 | PIO1_8 — GPIO port 1 pin 8 with alternate functions |
| 引脚 10 | PIO1_9 — GPIO port 1 pin 9 with alternate functions |
| 引脚 11 | VDDA — Analog supply (ADC and reference) |
| 引脚 12 | VSSA — Analog ground |
| 引脚 13 | PIO0_16 — GPIO port 0 pin 16 with alternate functions |
| 引脚 14 | PIO0_17 — GPIO port 0 pin 17 with alternate functions |
| 引脚 15 | PIO0_18 — GPIO port 0 pin 18 with alternate functions |
| 引脚 16 | PIO0_19 — GPIO port 0 pin 19 with alternate functions |
| 引脚 17 | PIO0_20 — GPIO port 0 pin 20 with alternate functions |
| 引脚 18 | PIO0_21 — GPIO port 0 pin 21 with alternate functions |
| 引脚 19 | PIO0_22 — GPIO port 0 pin 22 with alternate functions |
| 引脚 20 | PIO0_23 — GPIO port 0 pin 23 with alternate functions |
| 引脚 21 | PIO0_24 — GPIO port 0 pin 24 with alternate functions |
| 引脚 22 | PIO0_25 — GPIO port 0 pin 25 with alternate functions |
| 引脚 23 | VDD — Digital core supply |
| 引脚 24 | VSS — Digital ground |
| 引脚 25 | PIO0_26 — GPIO port 0 pin 26 with alternate functions |
| 引脚 26 | PIO0_27 — GPIO port 0 pin 27 with alternate functions |
| 引脚 27 | PIO0_28 — GPIO port 0 pin 28 with alternate functions |
| 引脚 28 | PIO0_29 — GPIO port 0 pin 29 with alternate functions |
| 引脚 29 | PIO0_30 — GPIO port 0 pin 30 with alternate functions |
| 引脚 30 | PIO0_31 — GPIO port 0 pin 31 with alternate functions |
| 引脚 31 | PIO1_10 — GPIO port 1 pin 10 with alternate functions |
| 引脚 32 | PIO1_11 — GPIO port 1 pin 11 with alternate functions |
| 引脚 33 | PIO1_12 — GPIO port 1 pin 12 with alternate functions |
| 引脚 34 | PIO1_13 — GPIO port 1 pin 13 with alternate functions |
| 引脚 35 | PIO1_14 — GPIO port 1 pin 14 with alternate functions |
| 引脚 36 | PIO1_15 — GPIO port 1 pin 15 with alternate functions |
| 引脚 37 | PIO1_16 — GPIO port 1 pin 16 with alternate functions |
| 引脚 38 | PIO1_17 — GPIO port 1 pin 17 with alternate functions |
| 引脚 39 | PIO1_18 — GPIO port 1 pin 18 with alternate functions |
| 引脚 40 | VDD — Digital core supply (second rail pin) |
| 引脚 41 | VSS — Digital ground (second ground pin) |
| 引脚 42 | PIO1_19 — GPIO port 1 pin 19 with alternate functions |
| 引脚 43 | PIO1_20 — GPIO port 1 pin 20 with alternate functions |
| 引脚 44 | PIO1_21 — GPIO port 1 pin 21 with alternate functions |
| 引脚 45 | PIO1_22 — GPIO port 1 pin 22 with alternate functions |
| 引脚 46 | PIO1_23 — GPIO port 1 pin 23 with alternate functions |
| 引脚 47 | PIO1_24 — GPIO port 1 pin 24 with alternate functions |
| 引脚 48 | PIO1_25 — GPIO port 1 pin 25 with alternate functions |
| 引脚 49 | PIO1_26 — GPIO port 1 pin 26 with alternate functions |
| 引脚 50 | PIO1_27 — GPIO port 1 pin 27 with alternate functions |
| 引脚 51 | PIO1_28 — GPIO port 1 pin 28 with alternate functions |
| 引脚 52 | PIO1_29 — GPIO port 1 pin 29 with alternate functions |
| 引脚 53 | PIO1_30 — GPIO port 1 pin 30 with alternate functions |
| 引脚 54 | PIO1_31 — GPIO port 1 pin 31 with alternate functions |
| 引脚 55 | VDD — Digital core supply (third rail pin) |
| 引脚 56 | VSS — Digital ground (third ground pin) |
| 引脚 57 | PIO0_0 — GPIO port 0 pin 0 with alternate functions |
| 引脚 58 | PIO0_1 — GPIO port 0 pin 1 with alternate functions |
| 引脚 59 | PIO0_2 — GPIO port 0 pin 2 with alternate functions |
| 引脚 60 | PIO0_3 — GPIO port 0 pin 3 with alternate functions |
| 引脚 61 | RESET — External reset input |
| 引脚 62 | PIO0_5 — GPIO port 0 pin 5 with alternate functions |
| 引脚 63 | PIO0_6 — GPIO port 0 pin 6 with alternate functions |
| 引脚 64 | PIO0_7 — GPIO port 0 pin 7 with alternate functions |
典型应用
LPC5526JBD64E 适用于 6 应用s: Industrial Automation and Motor Control, IoT Edge Nodes with Secure Boot, Consumer Appliances and White Goods, Embedded Sensing and Data Acquisition, Building Automation and HVAC Control, USB Peripherals and HID Devices.
Industrial Automation and Motor Control
The LPC5526JBD64E fits industrial control nodes because its 150 MHz Cortex-M33 core executes field-oriented control loops and multi-axis sequencing that 100 MHz-class M4 MCUs cannot sustain, while the 256 KB flash holds communication stacks and control firmware together. In a typical drive, the MCU runs the current loop at PWM frequency, processing ADC samples with DSP-class arithmetic; the MPU isolates the safety-critical control task from the protocol stack. TrustZone can further partition a secure bootloader from the application. Using the 64-HTQFP footprint shared across the LPC552x family, one PCB supports both 256 KB (LPC5526) and larger-flash (LPC5528) builds, de-risking firmware growth over the product lifecycle.
推荐
IoT Edge Nodes with Secure Boot
For IoT endpoints, the LPC5526JBD64E provides Arm TrustZone hardware isolation so cryptographic keys and secure firmware-update code stay separated from user applications, a key requirement for device identity in connected products. The 150 MHz core leaves ample margin for TLS stacks, JSON parsing, and sensor fusion alongside the main application, and 256 KB flash accommodates a full wireless or wired protocol stack. In deployment, the MCU runs the application in the non-secure world while secure-world code verifies signatures on every over-the-air update. Pairing with the LPC55S26 secure-series variant in the same pinout lets a single hardware design offer standard and hardended-security SKUs without board changes.
推荐
Consumer Appliances and White Goods
Home appliance controllers benefit from the LPC5526JBD64E's balance of cost and performance: the 150 MHz core handles BLDC compressor/fan control, UI processing, and connectivity bridging in one chip, while 256 KB flash stores multiple operating modes and localization data. The 40 nm process keeps unit cost competitive at the roughly $4.30 qty-1 / $2.95-at-1000 price level as of 2026-10-12. The MSL 3, 260 C / 30 s reflow rating is compatible with standard lead-free SMT assembly lines used in appliance manufacturing. Because all JBD64 family members share the footprint, appliance OEMs can scale memory across product tiers using one PCB layout.
推荐
Embedded Sensing and Data Acquisition
The LPC5526JBD64E serves mixed-signal acquisition front ends: the 150 MHz Cortex-M33 applies digital filtering, calibration, and linearization to ADC streams in real time, with the NVIC supporting deterministic low-latency sample interrupts and an NMI input with selectable sources for hard fault handling. The 256 KB flash retains calibration tables and compensation curves on-chip. In a typical chain, an external precision ADC streams samples over SPI while the MCU performs windowing and threshold detection before forwarding results. The MPU lets designers firewall acquisition buffers from communication code, improving reliability in long-duty-cycle monitoring instruments.
推荐
Building Automation and HVAC Control
HVAC and building controllers use the LPC5526JBD64E to run control algorithms (PID loops for temperature/pressure), BACnet/Modbus stacks, and local scheduling simultaneously - the 150 MHz core with 256 KB flash covers all three without an external processor. TrustZone protects commissioning credentials and network keys, important in commercial building networks. The 64-HTQFP 10x10 mm package offers sufficient I/O count for sensor inputs, damper/valve drivers, and display interfaces in a hand-solderable QFP footprint favored for field-serviceable controllers. Family pin-compatibility allows the same PCB to serve thermostat, AHU controller, and sensor-bridge variants with different LPC552x memory options.
推荐
USB Peripherals and HID Devices
The LPC552x family integrates USB device capability (per NXP family documentation), letting the LPC5526JBD64E implement USB HID, CDC, or vendor-class peripherals directly - for example, industrial HMI panels, test-instrument front panels, and configurable input devices. The 150 MHz core processes USB transactions plus display refresh and touch scanning concurrently, while 256 KB flash stores descriptors, configuration profiles, and firmware-update code. TrustZone can secure the USB firmware-update path against malicious re-flashing. The 40 nm process supports the low idle power expected in always-plugged USB accessories. Verify the exact USB PHY class support in the manufacturer datasheet for your target speed.
推荐
推荐产品汇总
工程参考数据： LPC5526JBD64E ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | LPC5526JBD64K | LPC5528JBD64E | LPC55S26JBD64E | LPC5516JBD64E |
|---|---|---|---|---|---|
| Package | 64-HTQFP (10x10 mm) | 64-HTQFP (10x10 mm) - same | 64-HTQFP (10x10 mm) - same | 64-HTQFP (10x10 mm) - same | 64-HTQFP (10x10 mm) - same |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Core | Arm Cortex-M33, 150 MHz | Arm Cortex-M33, 150 MHz | Arm Cortex-M33, 150 MHz | Arm Cortex-M33, 150 MHz | Arm Cortex-M33, 150 MHz |
| Flash Memory | 256KB | 256KB | Larger flash (verify in datasheet) | 256KB-class | Reduced (verify in datasheet) |
| Security | TrustZone (Armv8-M) | TrustZone (Armv8-M) | TrustZone (Armv8-M) | TrustZone + enhanced secure boot/key management | TrustZone (reduced feature set) |
| Lifecycle Status | Active | Active | Active | Active | Active |
| Package Match | Reference | Pin-to-pin identical | Pin-to-pin identical | Pin-to-pin identical | Pin-to-pin identical |
关键差异点
- First general-purpose Cortex-M33-based MCU series （对比 LPC5516JBD64E)
- Footprint-preserving memory upgrade path （对比 LPC5528JBD64E)
- Hardware security partitioning （对比 Older Cortex-M4 LPC54xxx parts)
设计说明
The 64-HTQFP (10x10 mm) has 0.5 mm lead pitch. Design the land pattern per the NXP datasheet footprint dimensions and keep a solid ground plane under the device. Connect all VDD pins (pins 23, 40, 55 in the standard map - verify against the datasheet pin configuration chapter) to the 3.3 V rail each with its own 100 nF decoupling capacitor placed within 2 mm of the pin, plus one bulk 4.7-10 uF capacitor near the package. Keep the VDDA/VSSA analog supply on a filtered, quiet island with a ferrite bead from the digital rail.
MSL 3 handling: after opening the moisture-barrier bag, floor life is limited to 168 hours before reflow (260 C peak, 30 s max). If exceeded, bake per standard SMD practice before assembly - otherwise popcorn cracking can occur during reflow. Also, when substituting family members (LPC5526 -> LPC5528/LPC55S26), re-verify RAM size and peripheral counts in the datasheet rather than assuming the firmware binary transfers unchanged.
Route high-speed clocks (crystal and internal 150 MHz derived signals) away from the ADC analog inputs near VDDA. Use a ground guard trace between analog and digital sections. For NMI input, add a pull resistor to the inactive level because it is a non-maskable, asynchronous source - spurious edges cannot be blocked in software. Decouple each VSS pin via via stitching directly to the ground plane rather than a shared trace.
合规信息
Terminal finish tin, JESD-609 code e3 (lead-free), per distributor specification data (Vyrian). RoHS compliance inferred from e3 finish and NXP standard practice; REACH and conflict-minerals status not stated in sourced data.
