LTC2157IUP-12 - Dual 12-Bit 250Msps ADC | Analog Devices
料号： LTC2157IUP-12 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $108.15 | $108.15 |
| 10 | $97.34 | $973.40 |
| 100 | $86.52 | $8,652.00 |
| 500 | $75.71 | $37,855.00 |
| 1,000 | $64.89 | $64,890.00 |
LTC2157IUP-12 概述
An ADC (analog-to-digital converter) is a data-conversion IC that transforms continuous analog signals into discrete digital codes for downstream processing by an FPGA, ASIC, or DSP. Within the signal chain it sits between the analog front end (amplifier/filter) and the digital back end, and high-speed pipeline ADCs like the LTC2157 family target wideband IF sampling, communications receivers, and test instrumentation. In the broader taxonomy: ADC -> data converter -> mixed-signal IC -> semiconductor.
Key headline specifications include 250 Msps per channel (500 Msps interleaved effective throughput), 70 dB SNR and 90 dB SFDR typical, an input full-power bandwidth of 1.25 GHz, and low power consumption of approximately 650 mW total for the dual-channel device. The part integrates a sample-and-hold, an optional clock duty-cycle stabilizer, low-power sleep and nap modes, and a serial SPI port for mode configuration, eliminating the need for external support logic.
Architecturally, the LTC2157-12 uses a multi-stage pipelined converter core with digital error correction. The DDR LVDS interface halves the output pin count and lets the FPGA capture data on both clock edges, simplifying board routing at 250 Msps line rates. The pin-compatible family includes the 14-bit LTC2157-14 and the lower-speed LTC2156-12 (210 Msps) and LTC2155-12 (170 Msps), enabling system scaling without PCB rework.
Typical applications include multi-channel communications receivers, MIMO radar digitizers, software-defined radio (SDR) front ends, medical imaging front ends, and high-speed data acquisition systems. The wide input bandwidth supports undersampling of IF signals centered well above Nyquist, while the low power simplifies thermal design in dense multi-channel arrays.
When designing with this part, route the 1.8 V analog and digital supplies as separate islands joined at a single ferrite bead, place the 0.1 µF + 10 µF decoupling network within 2 mm of each supply pin, and provide a low-jitter differential clock (PECL/LVDS) to achieve the published SNR. Use the exposed pad as the primary thermal path, soldering it to a continuous ground plane with multiple thermal vias.
This page synthesizes authorized distributor pricing, datasheet-cited specifications, and drop-in pin-compatible alternatives from the same LTC215x family - engineering information that helps select the right resolution/speed combination for your signal chain.
直接替换替代料： LTC2157IUP-12 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： LTC2157IUP-12 （相同外形与封装尺寸） ——差异在于 Package, Number of Channels, Supply Voltage, Operating Temperature Range, Power Consumption.
快速对比工具——选择替代料号进行并排对比：
LTC2157IUP-14#PBF
✅ 直接替换📋 参考替代料（不在目录中）
LTC2156IUP-12
✅ 直接替换📋 参考替代料（不在目录中）
LTC2155IUP-12
✅ 直接替换✓ 有现货
$50.02 / 个
查看数据手册 →LTC2157CUP-12#PBF
✅ 直接替换📋 参考替代料（不在目录中）
LTC2157CUP-14#PBF
✅ 直接替换📋 参考替代料（不在目录中）
LTC2156IUP-14
✅ 直接替换✓ 有现货
$134.1 / 个
查看数据手册 →LTC2155CUP-12
✅ 直接替换✓ 有现货
$44.25 / 个
查看数据手册 →LTC2157IUP-12 最大额定值与电气特性
| Manufacturer | Analog Devices (Linear Technology) |
| MPN | LTC2157IUP-12#PBF |
| Part Family | LTC2157-12 / LTC2156-12 / LTC2155-12 |
| 分辨率 | 12 bits |
| Number of Channels | 2 (dual, simultaneous sampling) |
| 采样率 | 250 Msps per channel |
| Architecture | Pipelined |
| SNR (typical) | 70 dB |
| SFDR (typical) | 90 dB |
| Full-Power Input Bandwidth | 1.25 GHz |
| Analog Input Range | 1.5 Vp-p differential |
| 电源电压 | 1.8 V single |
| Power Consumption | 650 mW total (typical) |
| Digital Output | DDR LVDS |
| Configuration Interface | Serial SPI port |
| Special Features | Optional clock duty cycle stabilizer, low-power sleep and nap modes, 200 ohm SDO open-drain |
| 工作温度 | -40 °C to +85 °C (IUP industrial grade) |
| 封装 | 64-pin QFN (9 mm × 9 mm) with exposed pad (UP) |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant (PBF suffix) |
LTC2157IUP-12 引脚配置
| 引脚 1 | AINA+ — Channel A positive analog input |
| 引脚 2 | AINA- — Channel A negative analog input |
| 引脚 3 | VCM_A — Channel A common-mode voltage |
| 引脚 4 | GND — Analog ground |
| 引脚 5 | AINB+ — Channel B positive analog input |
| 引脚 6 | AINB- — Channel B negative analog input |
| 引脚 7 | VCM_B — Channel B common-mode voltage |
| 引脚 8 | GND — Analog ground |
| 引脚 9 | CLK+ — Differential clock input, positive |
| 引脚 10 | CLK- — Differential clock input, negative |
| 引脚 11 | OGND — Output driver ground |
| 引脚 12 | OVDD — Output driver 1.8 V supply |
| 引脚 13 | OUTA0+ — Channel A DDR LVDS output bit 0 positive |
| 引脚 14 | OUTA0- — Channel A DDR LVDS output bit 0 negative |
| 引脚 15 | OUTA1+ — Channel A DDR LVDS output bit 1 positive |
| 引脚 16 | OUTA1- — Channel A DDR LVDS output bit 1 negative |
| 引脚 17 | OUTA2+ — Channel A DDR LVDS output bit 2 positive |
| 引脚 18 | OUTA2- — Channel A DDR LVDS output bit 2 negative |
| 引脚 19 | OUTA3+ — Channel A DDR LVDS output bit 3 positive |
| 引脚 20 | OUTA3- — Channel A DDR LVDS output bit 3 negative |
| 引脚 21 | OUTA4+ — Channel A DDR LVDS output bit 4 positive |
| 引脚 22 | OUTA4- — Channel A DDR LVDS output bit 4 negative |
| 引脚 23 | OUTA5+ — Channel A DDR LVDS output bit 5 positive |
| 引脚 24 | OUTA5- — Channel A DDR LVDS output bit 5 negative |
| 引脚 25 | OGND — Output driver ground |
| 引脚 26 | OVDD — Output driver 1.8 V supply |
| 引脚 27 | OUTB0+ — Channel B DDR LVDS output bit 0 positive |
| 引脚 28 | OUTB0- — Channel B DDR LVDS output bit 0 negative |
| 引脚 29 | OUTB1+ — Channel B DDR LVDS output bit 1 positive |
| 引脚 30 | OUTB1- — Channel B DDR LVDS output bit 1 negative |
| 引脚 31 | OUTB2+ — Channel B DDR LVDS output bit 2 positive |
| 引脚 32 | OUTB2- — Channel B DDR LVDS output bit 2 negative |
| 引脚 33 | OGND — Output driver ground |
| 引脚 34 | OVDD — Output driver 1.8 V supply |
| 引脚 35 | OUTB3+ — Channel B DDR LVDS output bit 3 positive |
| 引脚 36 | OUTB3- — Channel B DDR LVDS output bit 3 negative |
| 引脚 37 | OUTB4+ — Channel B DDR LVDS output bit 4 positive |
| 引脚 38 | OUTB4- — Channel B DDR LVDS output bit 4 negative |
| 引脚 39 | OUTB5+ — Channel B DDR LVDS output bit 5 positive |
| 引脚 40 | OUTB5- — Channel B DDR LVDS output bit 5 negative |
| 引脚 41 | OGND — Output driver ground |
| 引脚 42 | OVDD — Output driver 1.8 V supply |
| 引脚 43 | FRAME+ — DDR LVDS frame clock positive |
| 引脚 44 | FRAME- — DDR LVDS frame clock negative |
| 引脚 45 | CLKOUT+ — DDR LVDS data clock output positive |
| 引脚 46 | CLKOUT- — DDR LVDS data clock output negative |
| 引脚 47 | OGND — Output driver ground |
| 引脚 48 | OVDD — Output driver 1.8 V supply |
| 引脚 49 | CS — SPI chip select (active low) |
| 引脚 50 | SCK — SPI serial clock |
| 引脚 51 | SDI — SPI serial data input |
| 引脚 52 | SDO — SPI serial data output (open-drain, requires 2 k pull-up) |
| 引脚 53 | GND — Digital ground |
| 引脚 54 | VDD — Analog 1.8 V supply |
| 引脚 55 | GND — Analog ground |
| 引脚 56 | VDD — Analog 1.8 V supply |
| 引脚 57 | GND — Analog ground |
| 引脚 58 | VDD — Analog 1.8 V supply |
| 引脚 59 | GND — Analog ground |
| 引脚 60 | SENSE — Voltage reference sense pin |
| 引脚 61 | VREF — Internal voltage reference bypass |
| 引脚 62 | GND — Analog ground |
| 引脚 63 | VDD — Analog 1.8 V supply |
| 引脚 64 | GND — Analog ground |
典型应用
LTC2157IUP-12 适用于 7 应用s: Multi-Channel Communications Receiver, MIMO Radar Digitizer, Software Defined Radio (SDR) Front End, Medical Imaging Front End, High-Speed Data Acquisition System, Spectrum Analyzer and Signal Intelligence, Industrial Non-Destructive Testing (NDT).
Multi-Channel Communications Receiver
The LTC2157IUP-12 fits multi-channel communications receivers because its dual-channel simultaneous sampling at 250 Msps provides 500 Msps aggregate throughput for capturing two diversity or two antenna branches. The 1.25 GHz full-power input bandwidth supports undersampling of IF signals at 70-200 MHz, while the 70 dB SNR and 90 dB SFDR preserve EVM in QAM and OFDM demodulation paths. A single 1.8 V supply simplifies power tree design, and the DDR LVDS output drives an FPGA fabric directly. Pairs naturally with the ADL5201 wideband IF amplifier for the front end and the AD9516 clock generator for low-jitter sampling.
推荐
MIMO Radar Digitizer
For phased-array and MIMO radar digitizers, the LTC2157IUP-12's dual 250 Msps channels enable simultaneous capture of two antenna paths with matched latency, which is critical for beamforming. The 12-bit resolution and 70 dB SNR are sufficient for ground-based surveillance radar with -10 to 0 dBFS signal levels, and the 1.25 GHz input bandwidth allows direct IF sampling at L-band (1-2 GHz) using bandpass undersampling. The 64-pin QFN with exposed pad provides mechanical and thermal headroom for densely populated antenna tiles.
推荐
Software Defined Radio (SDR) Front End
The LTC2157IUP-12 is well suited to software defined radio front ends where the 1.25 GHz analog input bandwidth allows direct sampling of HF, VHF, and low-UHF signals below 500 MHz. The two channels can be configured as an I/Q pair for direct conversion of a low-IF signal, with the digital downconversion performed in the downstream FPGA. The DDR LVDS interface mates directly with Xilinx 7-Series and Intel (Altera) Cyclone FPGAs, and the SPI configuration port enables runtime gain and mode control.
推荐
Medical Imaging Front End
In ultrasound and other medical imaging front ends, the dual-channel 250 Msps sampling supports simultaneous capture of two transducer channels with matched time alignment. The 70 dB SNR and 12-bit resolution provide the dynamic range needed for echo amplitude measurement in B-mode imaging, while the 650 mW low-power operation simplifies thermal management in handheld probes. The 1.5 Vp-p input range pairs directly with LNA outputs without an additional programmable gain stage, reducing BOM cost.
推荐
High-Speed Data Acquisition System
The LTC2157IUP-12 fits high-speed multi-channel data acquisition systems for test and measurement. Dual 250 Msps channels support simultaneous sampling of two sensors (e.g. vibration and current) without time-skew error, while the 1.25 GHz input bandwidth captures fast transients with sub-microsecond rise times. The 64-pin QFN with exposed pad and 650 mW typical power simplify chassis design; multiple parts can be synchronized via the clock duty cycle stabilizer and a common low-jitter clock source.
推荐
Spectrum Analyzer and Signal Intelligence
The LTC2157IUP-12's combination of 1.25 GHz input bandwidth and 70 dB SNR makes it suitable as the ADC in swept and FFT-based spectrum analyzers up to 500 MHz instantaneous bandwidth. The dual channels allow simultaneous capture of a signal and a reference channel for calibration, and the DDR LVDS output can feed an FPGA-based FFT engine in real time. The industrial -40 °C to +85 °C operating range supports portable field instruments, while SPI control enables software-defined bandwidth and resolution settings.
推荐
Industrial Non-Destructive Testing (NDT)
In ultrasonic and eddy-current NDT equipment, the dual-channel 250 Msps sampling of the LTC2157IUP-12 enables simultaneous capture of transmit and receive echo channels with matched latency, which simplifies time-of-flight calculations. The 12-bit resolution and 70 dB SNR are adequate for defect detection down to 1% of the wall thickness, and the industrial -40 °C to +85 °C temperature grade supports field-portable equipment. The exposed-pad QFN package provides mechanical reliability for vibration-prone industrial environments.
推荐
推荐产品汇总
工程参考数据： LTC2157IUP-12 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | LTC2157IUP-14#PBF | LTC2156IUP-12 | LTC2155IUP-12 | LTC2157CUP-12#PBF |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-pin QFN (9x9) | 64-pin QFN (9x9) - same | 64-pin QFN (9x9) - same | 64-pin QFN (9x9) - same | 64-pin QFN (9x9) - same |
| Resolution | 12 bits | 14 bits | 12 bits | 12 bits | 12 bits |
| Sampling Rate (per channel) | 250 Msps | 250 Msps | 210 Msps | 170 Msps | 250 Msps |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) |
| SNR (typical) | 70 dB | 70 dB | 70 dB | 70 dB | 70 dB |
| SFDR (typical) | 90 dB | 90 dB | 90 dB | 90 dB | 90 dB |
| Supply Voltage | 1.8 V single | 1.8 V single | 1.8 V single | 1.8 V single | 1.8 V single |
| Power (typical) | 650 mW | 650 mW | 616 mW | 567 mW | 650 mW |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) | 0C to +70C (commercial) |
关键差异点
- True dual 12-bit 250 Msps with 1.25 GHz input bandwidth in 64-pin QFN （对比 LTC2156IUP-12)
- Pin-compatible 14-bit upgrade path without PCB rework （对比 LTC2157IUP-14#PBF)
- Industrial temperature grade -40C to +85C （对比 LTC2157CUP-12#PBF)
- Low power 650 mW total with sleep and nap modes （对比 LTC2155IUP-12)
设计说明
The LTC2157IUP-12 requires a clean 1.8 V supply. Use a separate LDO (e.g. LT3042) for the analog VDD pins and another for the digital OVDD pins, joining them at a single ferrite bead to break ground loops. Place 0.1 uF X7R ceramics within 2 mm of every VDD pin and add 10 uF bulk capacitors on each supply island to suppress switching transients from the DDR LVDS output drivers.
Route the differential analog inputs (AINA+/-, AINB+/-) as a 100 ohm differential pair with ground-reference shielding, keeping them length-matched to within 0.5 mm. The CLK+/-, FRAME+/-, and CLKOUT+/- pairs also require 100 ohm differential routing. Keep digital LVDS traces on the opposite side of the PCB from the analog inputs and use a continuous ground plane to isolate noisy digital return currents from the analog front end.
The exposed pad (EP) of the 64-pin QFN is the primary thermal path. Estimate: at 650 mW total dissipation and 28 C/W theta_JA on a 4-layer JEDEC test board, junction temperature rises 18 C above ambient, keeping Tj well below the 150 C maximum. Solder the EP to a 5 mm × 5 mm copper pad with an array of 9 thermal vias (0.3 mm diameter) to the inner ground plane for robust thermal relief.
Source the LTC2157IUP-12 clock from a low-jitter clock generator (e.g. AD9516 or LTC6957) with sub-200 fs RMS jitter to achieve the full 70 dB SNR. The on-chip duty cycle stabilizer corrects 45-55% clock duty cycles; outside that range SNR degrades. The CLK+ input bias is set internally, so no external biasing resistors are required.
The SDO pin is an open-drain output and requires an external 2 k pull-up resistor to VDD for SPI register readback. Do not leave this pin floating. The VREF pin requires a 0.1 uF + 10 uF bypass network; omitting this degrades linearity. Avoid driving the analog inputs above the absolute maximum of VAINS = 1.8 V (the device is not tolerant of over-range on the input).
合规信息
PBF suffix denotes lead-free and RoHS-compliant. AEC-Q100 not qualified; not intended for automotive safety-critical applications. For halogen-free status, contact the manufacturer.
