LTC2159CUK - 16-Bit 20Msps Low Power ADC | Analog Devices
料号： LTC2159CUK ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $40.7 | $40.70 |
| 10 | $38.7 | $387.00 |
| 100 | $34.95 | $3,495.00 |
| 500 | $31.85 | $15,925.00 |
| 1,000 | $28.75 | $28,750.00 |
LTC2159CUK 概述
A pipelined ADC is a high-speed sampling converter that uses multiple cascaded low-resolution flash stages and a digital correction engine to deliver high bit resolution at sample rates from a few MHz to several hundred MHz. Within the broader converter taxonomy, the LTC2159CUK belongs to the successive-approximation-adjacent high-speed family that sits between precision SAR ADCs (>1 Msps, low noise) and ultra-high-speed flash ADCs (>1 Gsps, low resolution). Pipeline ADCs trade latency for throughput and are the de-facto standard for wideband IF sampling, software-defined radio, and digital oscilloscope front ends.
Key differentiating specifications include 77 dB SNR at baseband, 90 dB SFDR, single 1.8 V analog supply operation, CMOS or DDR LVDS digital outputs with a separate 1.2 V to 1.8 V output supply, and very low power consumption (per the datasheet, total power is approximately one third of competing 16-bit/20 Msps parts). The integrated input network simplifies front-end design, and an internal clock duty-cycle stabilizer preserves AC performance even with poor clock sources.
Architecturally, the part combines a fully differential input buffer, a multi-stage switched-capacitor pipeline, and an LVDS/CMOS serializer, all clocked by a single-ended or differential encoding input. Digital-output formatting is selectable: full-rate CMOS, double-data-rate CMOS, or double-data-rate LVDS to ease interfacing with FPGAs and ASICs of varying I/O standards.
Typical applications include high-end communications receivers (LTE/3G base-station digitizers), radar IF sampling, cable-infrastructure head-ends, medical imaging (ultrasound I/Q demodulation), and high-density portable test instruments. For each of these, the combination of 16-bit resolution, 20 Msps, low power, and small 7 mm x 7 mm QFN footprint reduces board area and thermal budget.
Design consideration: when digitizing signals above the first Nyquist, ensure the front-end anti-alias filter has stop-band attenuation beyond 77 dB over the relevant image band, and provide a low-jitter clock to preserve SNR. At higher input frequencies, SNR degrades predictably, so select the input drive network to match the recommended source impedance.
This page synthesizes distributor pricing, packaged variants, and cross-reference alternatives that complement what is shown on the manufacturer product page.
直接替换替代料： LTC2159CUK ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： LTC2159CUK （相同外形与封装尺寸） ——差异在于 SNR, Resolution, Package, Sampling Rate, SFDR.
快速对比工具——选择替代料号进行并排对比：
LTC2158CUK
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
LTC2160CUK
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
LTC2122CUK
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$83 / 个
查看数据手册 →LTC2155CUP-12
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$44.25 / 个
查看数据手册 →LTC2156IUP-14
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$134.1 / 个
查看数据手册 →LTC2159CUK 最大额定值与电气特性
| 分辨率 | 16 bit |
| Sample Rate | 20 Msps |
| Number of Input Channels | 1 |
| Architecture | Pipelined |
| SNR | 77 dB |
| SFDR | 90 dB |
| Analog Supply Voltage | 1.8 V |
| Digital Output Supply Range | 1.2 V to 1.8 V |
| Digital Output Modes | CMOS / DDR CMOS / DDR LVDS |
| Input Type | Differential |
| 封装 | 48-lead QFN (7 mm x 7 mm) |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant |
| Lead-Free | Yes (PBF suffix) |
LTC2159CUK 48-lead qfn (7 mm x 7 mm) 引脚配置指南
LTC2159CUK（48-lead qfn (7 mm x 7 mm) 封装）的引脚配置。 该模拟元件具有输入、输出和电源引脚。请参阅制造商数据手册以了解失调调零、补偿和使能引脚配置。适用于信号调理和放大器电路。
暂无详细引脚数据： LTC2159CUK.
请参阅 数据手册 以查看完整引脚配置。
典型应用
LTC2159CUK 适用于 7 应用s: Communications Receiver IF Sampling, Radar IF Digitization, Medical Ultrasound I/Q Demodulation, Cable Infrastructure Head-End Digitizer, Portable Test and Measurement Instrument, Software Defined Radio (SDR) Receiver Front End, Wideband Data Acquisition Module.
Communications Receiver IF Sampling
The LTC2159CUK's 16-bit resolution and 20 Msps throughput, paired with 77 dB SNR and 90 dB SFDR, suit it to digitizing intermediate frequencies in LTE and 3G base-station receivers. Placed after the analog mixing stage, it samples the IF at 20 Msps with very low power dissipation, easing thermal budget in dense multi-channel systems. According to the datasheet, the differential input and integrated front-end network simplify the anti-alias filter design and reduce BOM count. Compared to a discrete 16-bit SAR running at the same rate, the LTC2159CUK's pipeline architecture delivers higher sustained throughput. Companion MPNs: a low-jitter clock generator (e.g., AD9523-1) and an FPGA with LVDS receivers (e.g., XC7A35T) complete the channel.
推荐
Radar IF Digitization
For radar IF digitization the LTC2159CUK offers 16-bit dynamic range with 90 dB SFDR, well-matched to the wide dynamic range of pulsed radar returns. At a 20 Msps sample rate, it captures multi-MHz signal envelopes with single-pass SNR integrity. Per the Analog Devices datasheet, the differential inputs reject common-mode noise from radar front-ends, while the optional LVDS output mode minimizes EMI across high-speed board traces. Compared to older 12-bit radar ADCs, the LTC2159CUK adds 4 effective bits of dynamic range, critical for resolving small targets next to large clutter. Companion MPNs: an LNA (e.g., HMC7178LP3GE) and an FPGA DSP fabric (e.g., XC7K325T) are typical co-designs.
推荐
Medical Ultrasound I/Q Demodulation
In ultrasound systems, the LTC2159CUK's low power and 16-bit resolution enable portable or handheld probe designs. Per the datasheet, the part operates from a single 1.8 V supply with a separate 1.2 V-1.8 V digital I/O rail, simplifying integration with low-power DSP processors. The differential input and 77 dB SNR preserve signal fidelity across the dynamic range of reflected ultrasound echoes. Placed after the I/Q demodulator, it samples the baseband at 20 Msps and outputs LVDS to the FPGA-based beamformer. Compared to larger resolution ultrasound ADCs, the LTC2159CUK's compact 48-QFN footprint reduces overall probe size and battery draw. Companion MPNs: AD8339 I/Q demodulator and a low-power FPGA.
推荐
Cable Infrastructure Head-End Digitizer
Cable downstream/upstream digitizers benefit from the LTC2159CUK's 77 dB SNR and 90 dB SFDR, which preserve QAM constellation integrity across hundreds of MHz of aggregated spectrum. According to the LTC2159 datasheet, the DDR LVDS output mode streamlines high-throughput data transfer to large FPGAs without adding parallel-data EMI. With 20 Msps throughput, the part captures multiple adjacent QAM carriers while keeping per-channel power dissipation low. Compared to older 12-bit cable ADCs, the LTC2159CUK adds critical margin for 1024-QAM and 4096-QAM modulation schemes. Companion MPNs: an FPGA with high-speed LVDS SERDES and a cable amplifier front-end.
推荐
Portable Test and Measurement Instrument
Handheld spectrum analyzers and portable digitizers benefit from the LTC2159CUK's low total power and 7 mm x 7 mm QFN footprint, both of which preserve battery life and reduce PCB area. According to the datasheet, the integrated input network simplifies front-end signal conditioning and saves BOM cost. The 16-bit/20 Msps combination suits digitizing audio-band to low-IF signals with 77 dB SNR. Compared to higher-speed pipeline ADCs, the LTC2159CUK is the right performance point for sub-10 MHz inputs and extends battery runtime. Companion MPNs: an op-amp front-end (e.g., AD8138) and a USB or Bluetooth bridge for data offload.
推荐
Software Defined Radio (SDR) Receiver Front End
The LTC2159CUK's combination of 16-bit resolution, 20 Msps rate, and configurable LVDS/CMOS outputs is well-suited to SDR receiver designs that digitize a low-IF directly from the mixer. Per the LTC2159 datasheet, the on-chip clock duty-cycle stabilizer preserves AC performance even with the variable-duty clocks produced by FPGA PLLs. The differential inputs reject common-mode noise from noisy SDR front-ends. Compared to 14-bit SDR ADCs, the LTC2159CUK adds 2-3 dB of dynamic range, expanding usable receiver sensitivity. Companion MPNs: an RF mixer (e.g., ADL5350) and a Zynq-series SDR SoC for processing.
推荐
Wideband Data Acquisition Module
For multi-channel wideband data-acquisition modules the LTC2159CUK's low per-channel power and small footprint let designers pack more channels onto a single board. According to the datasheet, the CMOS output mode reduces digital power in board-level designs where LVDS is unnecessary. 16-bit resolution at 20 Msps with 77 dB SNR is sufficient for vibration analysis, acoustic emission monitoring, and industrial ultrasound. Per the Analog Devices datasheet, the internal clock duty-cycle stabilizer simplifies PCB clock-tree design. Companion MPNs: a precision front-end op-amp (e.g., AD8255) and an FPGA.
推荐
推荐产品汇总
工程参考数据： LTC2159CUK ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | LTC2158CUK | LTC2160CUK | LTC2122CUK | LTC2155CUP-12 | LTC2156IUP-14 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 48-QFN (7x7) | 48-QFN (7x7) - same | 48-QFN (7x7) - same | 48-QFN (7x7) - same | 48-QFN (7x7) - same | 48-QFN (7x7) - same |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 14 bit | 14 bit |
| Sample Rate | 20 Msps | 20 Msps (dual-channel) | 25 Msps | 10 Msps | 125 Msps | 80 Msps |
| Channels | 1 | 2 | 1 | 1 | 1 | 1 |
| Analog Supply | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Digital Output Modes | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS |
关键差异点
- Combines 16-bit resolution, 20 Msps, and 77 dB SNR in a 48-QFN with very low power （对比 LTC2155CUP-12)
- Single-channel 16-bit 20 Msps with CMOS and DDR LVDS output options （对比 LTC2158CUK)
- 20 Msps sample rate with separate analog and digital supplies （对比 LTC2122CUK)
设计说明
Estimated routing from a 16-bit ADC at 20 Msps DDR LVDS: keep digital output traces matched within 0.5 mm and routed over a continuous reference plane. Per the LTC2159 datasheet, the LVDS output swing is approximately 350 mV; route both P/N pairs as a 100 ohm differential microstrip. Keep the analog input traces short and matched to maintain the 77 dB SNR figure.
Estimate: at 20 Msps with a 50 MHz input, sample-clock jitter must stay below 1 ps rms to avoid degrading the 77 dB SNR floor by more than 1 dB. Per the LTC2159 datasheet, use a low-jitter clock source such as the AD9523-1 with the internal clock duty-cycle stabilizer enabled. Do not drive the encode input with a long CMOS trace; convert to a differential LVPECL or LVDS source first.
Per the LTC2159 datasheet, the analog 1.8 V supply draws the bulk of the ADC power; the digital output supply (1.2 V to 1.8 V) power scales with output mode and clock rate. Use a ferrite bead plus bulk/ceramic decoupling network on each supply pin, and tie the exposed pad (EP) to a solid ground plane for both thermal dissipation and ground return. Avoid routing digital outputs across the analog supply region.
合规信息
Lead-free per #PBF suffix; RoHS/REACH statements from Analog Devices product page. No AEC-Q100 automotive qualification - see industrial-temp options in the alternatives list.
