LTC2161CUK - 16-Bit 40Msps Low Power ADC | Analog Devices
料号： LTC2161CUK ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $48.5 | $48.50 |
| 10 | $45.78 | $457.80 |
| 100 | $43.1 | $4,310.00 |
| 500 | $41.55 | $20,775.00 |
| 1,000 | $40.69 | $40,690.00 |
LTC2161CUK 概述
An ADC (analog-to-digital converter) is a semiconductor device that converts continuous analog voltage signals into discrete digital codes, forming the essential bridge between the analog sensor/frontend world and the digital signal-processing/back-end world. Within the converter hierarchy, the LTC2161 belongs to the pipelined-architecture family, which subdivides the conversion into multiple low-resolution stages to balance speed, resolution, and power efficiency. Pipelined ADCs > successive-approximation ADCs in speed > analog-to-digital converters > data converters > signal-chain ICs > semiconductors. The 16-bit resolution with 40 Msps sampling makes this part appropriate for instrumentation, communications, and industrial imaging where both dynamic range and acquisition speed matter.
Key features of the LTC2161 include pin-selectable single-ended or differential analog inputs, programmable digital output formats including CMOS and LVDS, internal bypass reference, and a low-power architecture that is significantly reduced compared with earlier-generation 16-bit pipelines. The differential analog input architecture provides excellent common-mode noise rejection, while the integrated duty-cycle stabilizer (DCS) compensates for clock duty-cycle distortion, easing clock-tree constraints in the host FPGA or ASIC.
Technically, the LTC2161 utilizes a multi-stage pipelined architecture with output error correction in each stage, followed by a digital post-processing block. This approach allows the device to deliver a true 16-bit code with maintained linearity across the full Nyquist band, supported by the 0.07 ps RMS jitter figure that keeps SNR high even on aggressive input slew rates. The 48-QFN package features an exposed thermal pad, which must be soldered to the PCB ground plane to provide the low-impedance return paths necessary for the LVDS/CMOS outputs and to dissipate converter self-heating.
Typical applications include high-end communications receivers, IF-sampling software-defined radios, medical imaging (ultrasound beamformers, MRI digitizers), instrumentation and oscilloscopes, multi-channel data acquisition systems, and spectrum analyzer front-ends. The wide dynamic range supports direct digitization of RF intermediate frequencies without a preceding mixer stage in many block diagrams.
Design tip: provide an ultra-low-jitter sampling clock to the LTC2161's CLK input, since jitter rather than quantisation often dominates SNR degradation at high input frequencies. When using LVDS outputs, maintain 100-ohm differential transmission-line terminations and match trace lengths to keep channel-to-channel skew within the FPGA capture window.
This page synthesizes distributor pricing, drop-in alternative candidates, and practical design notes that are not duplicated in the manufacturer datasheet alone, supporting faster component selection and sourcing decisions.
直接替换替代料： LTC2161CUK ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： LTC2161CUK （相同外形与封装尺寸） ——差异在于 Resolution, SFDR, SNR, Architecture, Number of Channels.
快速对比工具——选择替代料号进行并排对比：
LTC2160CUK
✅ 直接替换📋 参考替代料（不在目录中）
LTC2162CUK
✅ 直接替换📋 参考替代料（不在目录中）
LTC2161IUK
✅ 直接替换📋 参考替代料（不在目录中）
LTC2161CUK#PBF
✅ 直接替换📋 参考替代料（不在目录中）
LTC2122CUK
✅ 直接替换✓ 有现货
$83 / 个
查看数据手册 →LTC2145CUP-12
✅ 直接替换✓ 有现货
$26.4 / 个
查看数据手册 →LTC2161CUK 最大额定值与电气特性
| 分辨率 | 16 bits |
| Sample Rate | 40 Msps |
| Architecture | Pipelined |
| Number of Channels | 1 |
| Input Type | Differential, Single-Ended (pin-selectable) |
| SNR | 77 dB |
| SFDR | 90 dB |
| Aperture Jitter | 0.07 ps RMS |
| Digital Output Format | CMOS / LVDS (programmable) |
| Reference Type | Internal |
| 工作温度范围 | 0C to +70C (C-grade) |
| 封装 | 48-QFN (7x7 mm) with exposed pad |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant (PBF suffix) |
| Lead-Free | Yes (PBF suffix) |
LTC2161CUK 引脚配置
| 引脚 1 | VDD — Analog 3.3V supply |
| 引脚 2 | GND — Ground |
| 引脚 3 | AIN+ — Analog input positive (differential) |
| 引脚 4 | AIN- — Analog input negative (differential) |
| 引脚 5 | VREF — Reference voltage bypass |
| 引脚 6 | GND — Ground |
| 引脚 7 | SENSE — Reference mode select |
| 引脚 8 | REFT — Reference top bypass |
| 引脚 9 | REFB — Reference bottom bypass |
| 引脚 10 | OGND — Digital output driver ground |
| 引脚 11 | OVDD — Digital output driver supply |
| 引脚 12 | DNC — Do not connect |
| 引脚 13 | DNC — Do not connect |
| 引脚 14 | D15 — Digital output bit 15 (MSB) |
| 引脚 15 | D14 — Digital output bit 14 |
| 引脚 16 | D13 — Digital output bit 13 |
| 引脚 17 | D12 — Digital output bit 12 |
| 引脚 18 | D11 — Digital output bit 11 |
| 引脚 19 | D10 — Digital output bit 10 |
| 引脚 20 | D9 — Digital output bit 9 |
| 引脚 21 | D8 — Digital output bit 8 |
| 引脚 22 | D7 — Digital output bit 7 |
| 引脚 23 | D6 — Digital output bit 6 |
| 引脚 24 | D5 — Digital output bit 5 |
| 引脚 25 | D4 — Digital output bit 4 |
| 引脚 26 | D3 — Digital output bit 3 |
| 引脚 27 | D2 — Digital output bit 2 |
| 引脚 28 | D1 — Digital output bit 1 |
| 引脚 29 | D0 — Digital output bit 0 (LSB, CMOS mode) |
| 引脚 30 | CLKOUT — Clock output for data capture (LVDS) |
| 引脚 31 | DNC — Do not connect (LVDS mode N/C) |
| 引脚 32 | D0+/DNC — LVDS bit 0 positive or N/C |
| 引脚 33 | D0-/DNC — LVDS bit 0 negative or N/C |
| 引脚 34 | DNC — Do not connect |
| 引脚 35 | MODE — Digital output mode select (CMOS/LVDS) |
| 引脚 36 | CS — Chip select / serial interface (per datasheet) |
| 引脚 37 | SDO — Serial data output |
| 引脚 38 | SCK — Serial clock |
| 引脚 39 | SDI — Serial data input |
| 引脚 40 | OGND — Digital output driver ground |
| 引脚 41 | OVDD — Digital output driver supply |
| 引脚 42 | DNC — Do not connect |
| 引脚 43 | DNC — Do not connect |
| 引脚 44 | CLK+ — Sampling clock positive |
| 引脚 45 | CLK- — Sampling clock negative / complement |
| 引脚 46 | VDD — Analog 3.3V supply |
| 引脚 47 | GND — Ground |
| 引脚 48 | GND — Ground |
| 引脚 EP | Exposed Pad — Thermal pad - solder to PCB ground plane |
典型应用
LTC2161CUK 适用于 6 应用s: Communications IF-Sampling Software-Defined Radio, Medical Ultrasound Beamformer, Test and Measurement Instrumentation, Industrial Multi-Channel Data Acquisition, Radar and Lidar Receiver Front-Ends, Spectrum Analyzer IF Digitization.
Communications IF-Sampling Software-Defined Radio
The LTC2161CUK digitizes wideband IF signals in communications receivers with its 16-bit resolution, 40 Msps sampling rate, and 77 dB SNR / 90 dB SFDR per the Analog Devices datasheet. The 0.07 ps RMS aperture jitter keeps SNR high at high input frequencies, enabling direct IF sampling without a preceding mixer. In a typical block diagram, the ADC follows an anti-alias filter and feeds samples directly into an FPGA-based DSP chain. The 48-QFN footprint simplifies PCB layout for multi-channel receiver cards.
推荐
Medical Ultrasound Beamformer
The LTC2161CUK provides 16-bit, 40 Msps conversion of receive channels in ultrasound beamformer front-ends, with its differential analog input rejecting common-mode noise from probe cables. Its 77 dB SNR contributes to the dynamic range needed to capture echoes from both deep tissue (low amplitude) and surface reflectors (high amplitude) within the same scan line. LVDS output mode supports high-density, multi-channel PCB routing in compact ultrasound carts, while CMOS mode is preferred for cost-optimized portable designs.
推荐
Test and Measurement Instrumentation
In oscilloscopes, spectrum analyzers, and data-acquisition chassis, the LTC2161CUK digitizes input signals with 16-bit resolution and 40 Msps throughput per the Analog Devices datasheet. Its 90 dB SFDR allows accurate measurement of small signals in the presence of large adjacent tones without spur overlap, which is critical for spurious-emission compliance testing. The 48-QFN exposed pad provides thermal dissipation for continuous high-throughput sampling, and its LVDS output mode supports clean integration with high-pin-count FPGA capture devices used in modern oscilloscope front-ends.
推荐
Industrial Multi-Channel Data Acquisition
Multi-channel data acquisition systems use the LTC2161CUK to digitize factory sensors, vibration pickups, and high-speed industrial control signals. Its 16-bit resolution and 40 Msps sampling capture the high-frequency content needed for predictive-maintenance vibration analysis, while the programmable CMOS or LVDS digital outputs simplify PCB design when scaling to 8, 16, or 32 channels per chassis. The commercial CUK temperature range (0C to +70C) is appropriate for indoor factory environments, and the lead-free PBF ordering variant supports RoHS compliance for European industrial customers.
推荐
Radar and Lidar Receiver Front-Ends
In radar receivers and lidar digitizer paths, the LTC2161CUK samples IF or baseband signals with 16-bit resolution and 77 dB SNR per the Analog Devices datasheet. The 0.07 ps RMS aperture jitter supports accurate phase-coherent sampling required for Doppler and synthetic-aperture-radar processing. Differential analog inputs reject common-mode noise from high-current transmitter pulses coupled through cabling, and the 48-QFN package provides a compact footprint for installation within space-constrained sensor heads and centralized processor enclosures.
推荐
Spectrum Analyzer IF Digitization
Spectrum analyzer IF digitization leverages the LTC2161CUK's 16-bit resolution, 40 Msps sample rate, and 90 dB SFDR to capture narrow IF bandwidths with both high dynamic range and low spurious content. The differential analog input rejects ground noise from the analyzer's analog mixing stages, and the CMOS/LVDS programmable output mode lets designers match the output interface to the FPGA or DSP backbone. The commercial CUK temperature grade is well suited to benchtop and rack-mounted laboratory environments where ambient temperature is regulated.
推荐
推荐产品汇总
工程参考数据： LTC2161CUK ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | LTC2160CUK | LTC2162CUK | LTC2161IUK | LTC2122CUK |
|---|---|---|---|---|---|
| Package | 48-QFN (7x7) | 48-QFN (7x7) - same | 48-QFN (7x7) - same | 48-QFN (7x7) - same | 48-QFN (7x7) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 16 bits | 16 bits | 16 bits | 14 bits | 12 bits |
| Sample Rate | 40 Msps | 25 Msps | 65 Msps | 40 Msps | 20 Msps |
| SNR | 77 dB | 77 dB | 76 dB | 77 dB | 75 dB |
| SFDR | 90 dB | 90 dB | 88 dB | 90 dB | 88 dB |
| Aperture Jitter | 0.07 ps RMS | 0.07 ps RMS | 0.07 ps RMS | 0.07 ps RMS | 0.07 ps RMS |
| Operating Temperature | 0C to +70C | 0C to +70C | 0C to +70C | -40C to +85C | 0C to +70C |
| Digital Output | CMOS / LVDS | CMOS / LVDS | CMOS / LVDS | CMOS / LVDS | CMOS / LVDS |
关键差异点
- True 16-bit resolution with 40 Msps throughput in 48-QFN （对比 LTC2122CUK)
- Commercial temperature grade option for indoor designs （对比 LTC2161IUK)
- Sample-rate scalability within the same pinout （对比 LTC2160CUK and LTC2162CUK)
设计说明
Provide an ultralow-jitter sampling clock to the LTC2161 CLK+/CLK- input, because aperture jitter (not quantisation) often dominates SNR degradation at high input frequencies. A poor clock source can erase the 0.07 ps RMS jitter benefit. Route clock traces short and matched, terminate at the receiver per LVDS conventions, and place clock-generation components away from noisy power stages. Estimated: at 100 MHz analog input, every 1 ps RMS of additional clock jitter reduces SNR by approximately 6 dB above the quantisation floor.
Solder the LTC2161's 48-QFN exposed thermal pad (EP) to a continuous PCB ground plane - this provides both the thermal path for self-heating and the low-impedance return for the analog front-end and digital output drivers. Use a via array beneath the pad (typically 4x4 to 6x6 vias) to conduct heat to inner copper planes. Keep analog input traces symmetric (matched length/width pairs) and surrounded by a ground pour to preserve the differential input's common-mode rejection above 60 dB.
Power the analog VDD and digital OVDD from separate, well-decoupled rails to prevent digital switching noise from coupling into the analog front-end. Place 10 uF bulk ceramic and 0.1 uF high-frequency bypass capacitors as close to each pin as possible, ideally on the same layer as the IC. Use an L-C or ferrite-bead pi-filter between the analog 3.3V plane and digital 3.3V plane, especially when the part is configured for LVDS outputs which draw substantial switching current at 40 Msps.
合规信息
Lead-free and RoHS-compliant per the PBF ordering suffix per the Analog Devices product page. Halogen-free status not explicitly stated in the verified web data and is set to unknown.