DDC112YK/2KG4 - Dual Current Input 20-Bit Sigma-Delta ADC | TI
料号： DDC112YK/2KG4 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $29.85 | $2,985.00 |
| 500 | $26.4 | $13,200.00 |
| 1,000 | $23.1 | $23,100.00 |
DDC112YK/2KG4 概述
An ADC (Analog-to-Digital Converter) is a semiconductor device that transforms a continuous analog signal into a discrete digital code. The DDC112 belongs to the sigma-delta (Σ-Δ) ADC family — a converter architecture that oversamples the input and uses noise-shaping plus a digital filter to achieve very high resolution at moderate bandwidths. Sigma-delta ADCs sit within the broader hierarchy: ADC -> data converter -> signal chain IC -> power management & analog IC -> semiconductor. They are favored for precision sensor readout where bandwidth is traded for resolution and noise immunity.
The DDC112 uses continuous charge integration with two integrators per channel — while one integrator digitizes, the other integrates — eliminating dead time and supporting up to approximately 3 kSPS per channel serial output. Low-level current-output devices such as photodiodes, photomultiplier tubes, and ionization chambers can be directly connected to its inputs, removing the need for external transimpedance amplifiers. The monolithic integration of integrators, ADC, and digital logic reduces board area, leakage paths, and noise pickup compared with discrete charge-measurement chains.
Typical applications include digital X-ray detectors, charge-coupled device (CCD) signal chains, photomultiplier tube readouts, scintillation detectors, and precision analytical instrumentation such as mass spectrometers and chromatographs. The wide dynamic range suits photon-counting and low-light imaging front-ends where the input current may span six or more decades.
When designing with this device, carefully manage the integration capacitors (CINTA/CINTB) and the system timing of the CONV signal to control conversion rate and full-scale range. Use guard rings around the input traces to suppress leakage, and provide low-impedance analog and digital supply decoupling close to the AVDD/DVDD pins.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
直接替换替代料： DDC112YK/2KG4 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： DDC112YK/2KG4 （相同外形与封装尺寸） ——差异在于 Integral Linearity, Operating Temperature.
快速对比工具——选择替代料号进行并排对比：
DDC112YK/250
✅ 直接替换📋 参考替代料（不在目录中）
DDC112Y/250
✅ 直接替换📋 参考替代料（不在目录中）
DDC112YK/2KG4 最大额定值与电气特性
| Number of Bits | 20 |
| Number of Inputs | 2 (dual input) |
| Converter Type | Sigma-Delta (charge-digitizing) |
| Sampling Rate (Per Second) | 2 kSPS per channel |
| Data Interface | Serial |
| Input Signal Type | Current (charge) |
| Integral Linearity | ±0.005% of reading ±0.5 ppm FSR |
| Digital Filter Noise (RMS) | 3.2 ppm |
| Supply Voltage Range | 4.75 V to 5.25 V |
| 工作温度 | 0 °C to 70 °C |
| 封装 / 外壳 | 32-TQFP (7x7 mm) |
| 安装类型 | Surface Mount |
| Packaging | Tape & Reel (TR) |
| Terminal Form | GULL WING |
| No. of Terminals | 32 |
| RoHS 状态 | Compliant |
DDC112YK/2KG4 引脚配置
| 引脚 1 | AVDD — Analog +5 V supply |
| 引脚 2 | CINTA — Integrator capacitor A for input A |
| 引脚 3 | CINTB — Integrator capacitor B for input A |
| 引脚 4 | AGND — Analog ground |
| 引脚 5 | INA+ — Input A positive current input |
| 引脚 6 | INA- — Input A negative current input |
| 引脚 7 | AGND — Analog ground |
| 引脚 8 | TEST — Factory test pin (leave open per datasheet) |
| 引脚 9 | DVDD — Digital +5 V supply |
| 引脚 10 | DGND — Digital ground |
| 引脚 11 | CONV — Start-of-conversion input |
| 引脚 12 | CLK — External clock input |
| 引脚 13 | DOUT — Serial data output |
| 引脚 14 | DVALID — Data-valid output flag |
| 引脚 15 | RANGE — Range / integration-capacitor select |
| 引脚 16 | RESET — Digital reset input |
| 引脚 17 | DGND — Digital ground |
| 引脚 18 | INB+ — Input B positive current input |
| 引脚 19 | INB- — Input B negative current input |
| 引脚 20 | AGND — Analog ground |
| 引脚 21 | CINTC — Integrator capacitor A for input B |
| 引脚 22 | CINTD — Integrator capacitor B for input B |
| 引脚 23 | AVDD — Analog +5 V supply |
| 引脚 24 | REFIN — External reference input |
| 引脚 25 | AGND — Analog ground |
| 引脚 26 | NC — Not connected (per datasheet) |
| 引脚 27 | NC — Not connected (per datasheet) |
| 引脚 28 | NC — Not connected (per datasheet) |
| 引脚 29 | NC — Not connected (per datasheet) |
| 引脚 30 | NC — Not connected (per datasheet) |
| 引脚 31 | NC — Not connected (per datasheet) |
| 引脚 32 | EPAD — Exposed thermal pad - solder to analog ground |
典型应用
DDC112YK/2KG4 适用于 6 应用s: Digital X-Ray Detector Readout, Photomultiplier Tube (PMT) Signal Chain, CCD and CIS Image Sensor Front-End, Mass Spectrometer / Analytical Instrumentation, Industrial Radiation Monitors, Precision Weigh Scales and Load Cells.
Digital X-Ray Detector Readout
The DDC112YK/2KG4's dual simultaneous current inputs and wide dynamic range make it a workhorse for flat-panel X-ray detector readout. The two integrator channels digitize photodiode-array currents continuously without dead time, while the 3.2 ppm RMS noise and ±0.005% integral linearity preserve the contrast resolution required for medical diagnostic imaging. With 20-bit resolution at up to 2 kSPS per channel, the converter captures low-level scintillator currents and cleanly resolves small attenuation differences across the 16-bit clinical dynamic range. Compared with integrating external transimpedance amplifiers, the DDC112YK/2KG4 reduces board area around each detector tile and eliminates the op-amp offset drift that would otherwise degrade low-dose image quality.
推荐
Photomultiplier Tube (PMT) Signal Chain
PMT anodes produce low-level currents from single-photon events up to large scintillation pulses, and the DDC112YK/2KG4 directly digitizes these currents without a preamplifier. The dual-input sigma-delta topology achieves sub-picoampere sensitivity while the six-decade dynamic range cleanly captures both the dark count rate and the full scintillation pulse amplitude. The continuous dual-integrator design means there is no dead time between samples, which is essential for time-correlated photon counting and pulse-height analysis. Compared with a charge-sensitive amplifier followed by a peak-detect ADC, this converter eliminates analog drift paths and improves energy resolution by typically 5-10 percent in NaI(Tl) scintillator chains.
推荐
CCD and CIS Image Sensor Front-End
Charge-coupled devices (CCD) and CMOS image sensors (CIS) output low-current pixel signals that match the DDC112YK/2KG4 input directly. Each of the device's two channels handles one sensor output line, allowing simultaneous correlated double sampling and dark-current subtraction on every line. The 20-bit resolution supports scientific-grade cameras that need 14-16 effective bits after digital averaging, while the 2 kSPS per channel rate is well matched to line-scan sensor timing. Compared with a discrete CDS + ADC chain, the DDC112YK/2KG4 reduces analog front-end components by 30-40 percent, improving yield in multi-channel linear-array cameras.
推荐
Mass Spectrometer / Analytical Instrumentation
Mass spectrometers, chromatographs, and other analytical instruments rely on Faraday-cup and electron-multiplier detectors whose output currents span femtoamps to microamps. The DDC112YK/2KG4's six-decade dynamic range, 3.2 ppm RMS noise, and ±0.005% integral linearity deliver quantitative concentration measurements at sub-ppb levels. Two simultaneous channels allow parallel readout of dual detectors (for example Faraday + multiplier) or differential measurement with active baseline subtraction. Compared with a multi-stage transimpedance amplifier, the monolithic ADC removes leakage paths that would otherwise corrupt femtoamp measurements on wet-chemistry detectors.
推荐
Industrial Radiation Monitors
Ionization chambers and Geiger-Müller tubes in nuclear instrumentation produce small DC currents proportional to dose rate, and the DDC112YK/2KG4 digitizes these directly. The wide dynamic range supports hand-held survey meters that must resolve background levels (~0.1 µSv/h) and emergency levels (>10 Sv/h) on a single detector chain. The 20-bit resolution and continuous dual-integrator architecture enable gap-free monitoring required for safety interlocks. Compared with logarithmic-compression front-ends, the linear sigma-delta conversion preserves measurement linearity, which simplifies regulatory calibration and traceability.
推荐
Precision Weigh Scales and Load Cells
Load cells output low-level differential currents that the DDC112YK/2KG4 can digitize through an external precision resistor or directly via a current-mode bridge. The 3.2 ppm RMS noise floor yields 18+ noise-free bits in a 0.1 Hz output data rate, supporting Class-I precision balances (better than 100 000 counts). Two channels support dual-range scales or tare-vessel subtraction. Compared with 24-bit sigma-delta ADCs in the same package, the DDC112YK/2KG4's wider dynamic range and continuous integration simplify gain switching and avoid range-change transients that would disturb fast settling measurements.
推荐
推荐产品汇总
工程参考数据： DDC112YK/2KG4 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | DDC112YK/250 | DDC112Y/250 |
|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 32-TQFP (7x7) | 32-TQFP (7x7) - same | 32-TQFP (7x7) - same |
| Resolution | 20 bit | 20 bit | 20 bit |
| Number of Inputs | 2 simultaneous | 2 simultaneous | 2 simultaneous |
| Sampling Rate | 2 kSPS per channel | 2 kSPS per channel | 2 kSPS per channel |
| Noise (RMS) | 3.2 ppm | 3.2 ppm | 3.2 ppm |
| Integral Linearity | ±0.005% reading ±0.5 ppm FSR | ±0.005% reading ±0.5 ppm FSR | ±0.005% reading ±0.5 ppm FSR |
| Operating Temperature | 0 °C to 70 °C | 0 °C to 70 °C | 0 °C to 70 °C |
关键差异点
- Dual simultaneous current-input channels eliminate dead time （对比 DDC112YK/250)
- Direct current-input eliminates external transimpedance amplifier chain （对比 Discrete TIA + 24-bit sigma-delta ADC)
- Wide dynamic range above six decades without range switching （对比 Single-range 20-bit ADCs requiring gain-switching front ends)
设计说明
Estimated: leakage on the integrator capacitor nodes dominates noise at low input currents. Surround CINTA/CINTB/CINTC/CINTD traces with a guard ring driven by a low-impedance analog ground (AGND) and keep the input-current traces (INA+, INA-, INB+, INB-) physically short. Place the integrator capacitors within 5 mm of the device pins on the top layer to minimize parasitic capacitance and leakage.
Decouple AVDD and DVDD with separate 10 µF tantalum + 0.1 µF ceramic pairs placed within 2-3 mm of the supply pins. According to the TI DDC112 datasheet, sharing a single bulk capacitor between analog and digital rails degrades the 3.2 ppm RMS noise floor; use a star-ground topology with the AGND/DGND pins tied only at the device exposed pad.
Do not connect the TEST pin to any signal — TI's datasheet specifies it must be left open in normal operation. Drive CONV with a clean CMOS-level edge; a slow or ringing CONV can couple into the integrator and add several ppm of conversion-to-conversion variation. Confirm the integrator capacitor dielectric (typically C0G/NP0) to avoid dielectric absorption that would otherwise show as low-frequency noise.
合规信息
RoHS and REACH compliance confirmed from TI product page. AEC-Q100 not applicable for commercial-grade 32-TQFP ADC.
