NTB0102GT,115 - 2-Bit Auto-Direction Level Translator | NXP
料号： NTB0102GT115 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $0.55 | $0.55 |
| 10 | $0.47 | $4.70 |
| 100 | $0.33 | $33.00 |
| 500 | $0.27 | $135.00 |
| 1,000 | $0.22 | $220.00 |
| 3,000 | $0.19 | $570.00 |
NTB0102GT115 概述
A dual-supply translating transceiver is a type of voltage level shifter within the broader logic IC family. Its role in the system hierarchy is to bridge digital domains operating at different supply voltages - for example a 1.8 V microcontroller port communicating with a 3.3 V peripheral. Unlike direction-controlled transceivers, auto direction sensing parts eliminate a DIR pin, using the data itself to determine signal flow, which simplifies firmware and board design.
Key features include a VCC(A) supply range of 1.2 V to 3.6 V and a VCC(B) range of 1.65 V to 3.6 V, supporting virtually any low-voltage logic pairing including 1.2 V to 3.3 V translation. The output enable (OE) input 3-states all I/Os when low, and partial power-down operation (Ioff) protects both supplies during power sequencing. The 100 Mbps throughput comfortably covers I2C-fast-class, SPI, UART, and general-purpose GPIO translation.
Architecturally, the NTB0102 uses a transmission-gate based topology with pull-up keepers on each I/O. Because the keepers are weak, bus holding is suitable for lightly capacitive lines; strongly driven push-pull sources on either side determine direction dynamically. This makes the part ideal for point-to-point links rather than heavily loaded multidrop buses.
Typical applications include microcontroller-to-peripheral GPIO and SPI translation, open-drain I2C and SMBus bus translation with appropriate pull-ups, and level shifting between low-voltage FPGA or SoC banks and 3.3 V system logic.
Design consideration: the weak bus keepers mean the NTB0102 is best suited to push-pull driven signals; for heavily loaded multidrop buses, consider the push-pull driver NTS0102 family variant instead.
This page synthesizes distributor pricing context, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, with all data verified as of 2026-10-19.
直接替换替代料： NTB0102GT115 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
快速对比工具——选择替代料号进行并排对比：
NTS0102GT,115
✅ 直接替换📋 参考替代料（不在目录中）
NTB0102GT,125
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
NTB0102GT115 最大额定值与电气特性
| 功能 | Dual-supply translating transceiver, auto direction sensing |
| Bit Width | 2-bit |
| 通道数 | 2 |
| Translation Type | Bidirectional |
| VCC(A) Supply Range | 1.2 V to 3.6 V |
| VCC(B) Supply Range | 1.65 V to 3.6 V |
| Maximum Data Rate | 100 Mbps |
| 输出类型 | 3-state |
| Output Enable | Yes (OE pin, 3-state when low) |
| Direction Control | Automatic (no DIR pin) |
| 封装 | 8-pin XSON, SOT833-1 (1.95 x 1 mm) |
| 安装类型 | Surface Mount |
| Ioff Partial Power-Down | Yes |
| RoHS 状态 | Compliant (,115 ordering code) |
| Packaging | Tape and Reel (T/R) |
NTB0102GT115 8-pin xson, sot833-1 (1.95 x 1 mm) 引脚配置指南
NTB0102GT115（8-pin xson, sot833-1 (1.95 x 1 mm) 封装）的引脚配置。 该数字 IC 包含 GPIO、通信接口（UART、SPI、I2C）和电源引脚。请参阅制造商数据手册以了解复用引脚功能和配置选项。对嵌入式系统设计和 PCB 布局至关重要。
暂无详细引脚数据： NTB0102GT115.
请参阅 数据手册 以查看完整引脚配置。
典型应用
NTB0102GT115 适用于 6 应用s: Microcontroller GPIO Level Translation, I2C and SMBus Bus Translation, SPI Signal Level Shifting, FPGA and SoC Bank-to-Bank Translation, Battery-Powered Portable and Wearable Devices, Industrial Control and Automation Interfaces.
Microcontroller GPIO Level Translation
The NTB0102GT,115 fits microcontroller GPIO translation because its 1.2 V to 3.6 V VCC(A) range covers the newest 1.2 V core-domain MCUs while VCC(B) reaches the 3.3 V peripheral domain, and its auto direction sensing removes the need for a DIR GPIO. In a typical link, VCC(A) ties to the MCU I/O rail and VCC(B) to the peripheral rail, with both An/Bn port pairs carrying bidirectional signals such as data or handshaking lines at up to 100 Mbps. The OE pin allows the bus to be 3-stated during reset so neither domain is back-driven while supplies are unstable. Because the internal keepers are weak, each line should be actively driven push-pull on at least one side; this makes the device ideal for point-to-point GPIO expansion between a low-voltage SoC and 3.3 V sensors or actuators with no firmware overhead.
推荐
I2C and SMBus Bus Translation
For I2C level translation, the NTB0102GT,115's open-drain-friendly, auto-direction architecture is a strong match: SDA naturally changes direction mid-transaction and the translator follows it without a DIR control line. Connect VCC(A) to the controller-side rail (as low as 1.2 V) and VCC(B) to the peripheral-side rail up to 3.6 V, and fit external pull-up resistors on both sides of each line, sized so the total bus capacitance keeps rise times within the target I2C speed class. The 100 Mbps throughput ceiling gives large margin for 400 kHz fast-mode and 1 MHz fast-mode-plus operation. During system power-up, holding OE low 3-states the bus and prevents latch-up through partially powered slaves. This application suits battery-powered designs where a 1.8 V PMIC-managed MCU must talk to 3.3 V EEPROMs, RTCs, or sensor hubs.
推荐
SPI Signal Level Shifting
SPI runs as point-to-point push-pull signals (SCLK, MOSI, MISO, CS), which the NTB0102GT,115 handles well at moderate clock rates up to roughly 30-50 MHz given its 100 Mbps channel rating. VCC(A) connects to the controller rail and VCC(B) to the 1.65 V-3.6 V peripheral rail, letting a 1.8 V MCU communicate with 3.3 V flash, displays, or RF modules. Because MISO reverses direction every transaction, the auto direction sensing eliminates explicit direction control that would otherwise be needed on that line. Keep traces short and pull-ups optional since the actively driven lines define levels. For SPI above 50 MHz or with heavy capacitive loading, the push-pull NTS0102GT,115 in the same footprint provides stronger edges; the two are footprint-compatible, so the layout can be reused if the design later needs higher speed.
推荐
FPGA and SoC Bank-to-Bank Translation
Modern FPGAs and SoCs expose I/O banks at 1.2 V, 1.8 V, or 2.5 V that must interoperate with legacy 3.3 V system logic, and the NTB0102GT,115 bridges exactly that gap: VCC(A) spans 1.2 V to 3.6 V on the low-voltage bank side, VCC(B) spans 1.65 V to 3.6 V on the system side. The 1.95 x 1 mm SOT833-1 footprint fits directly beside dense BGA escape routing where board area is scarce. Its Ioff partial power-down behavior means the FPGA bank can be powered down for reconfiguration without corrupting or back-powering the 3.3 V domain, and OE can 3-state the bridge during configuration. Each translated GPIO, status, or interrupt line operates up to 100 Mbps, comfortably covering configuration-done/status handshakes and medium-speed parallel status buses in industrial and communications equipment.
推荐
Battery-Powered Portable and Wearable Devices
Portable and wearable products commonly mix a 1.2 V-1.8 V application processor domain with 3.3 V sensors, haptics, or NFC front-ends, and the NTB0102GT,115 suits this because of its tiny 1.95 x 1 mm XSON-8 SOT833-1 package, one of the smallest footprints in level translation, plus its low static power operation across the 1.2 V-3.6 V and 1.65 V-3.6 V supply windows. The OE pin allows the micro to gate the bridge entirely during deep sleep, 3-stating both domains so leakage through the translator is eliminated - a meaningful battery-life contribution in wearables that spend most of their life suspended. Auto direction sensing removes a GPIO from the already pin-constrained mobile design. Typical links include a 1.8 V sensor-hub I2C bus to 3.3 V accessories, or bidirectional interrupt/data lines between the PMIC domain and the main battery gauge.
推荐
Industrial Control and Automation Interfaces
In industrial control boards, a 3.3 V or 1.8 V microcontroller must frequently drive 3.3 V-to-5 V-tolerant peripheral logic, optocoupler inputs, and fieldbus transceivers, and the NTB0102GT,115 serves as the rail bridge thanks to its wide 1.2 V-3.6 V / 1.65 V-3.6 V supply window and 100 Mbps bandwidth that covers UART, SPI, and parallel status signaling used on PLC I/O cards. The 3-state OE input supports hot-swapping of I/O cards: the carrier holds OE low until the card is seated and its local supply is valid, preventing contention or back-driving. Partial power-down Ioff behavior protects the control rail when a card is de-energized for maintenance. For noise-prone factory environments, keep translated traces short and referenced to a clean ground, and rely on the translator's defined levels rather than marginal direct connections between mismatched rails.
推荐
推荐产品汇总
工程参考数据： NTB0102GT115 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | NTS0102GT,115 | NTB0102GT,125 |
|---|---|---|---|
| Package | 8-XSON (SOT833-1) 1.95 x 1 mm | 8-XSON (SOT833-1) - same | 8-XSON (SOT833-1) - same |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Bit Width / Channels | 2-bit, 2 channel | 2-bit, 2 channel | 2-bit, 2 channel |
| VCC(A) Range | 1.2 V to 3.6 V | 1.2 V to 3.6 V | 1.2 V to 3.6 V |
| VCC(B) Range | 1.65 V to 3.6 V | 1.65 V to 3.6 V | 1.65 V to 3.6 V |
| Max Data Rate | 100 Mbps | 100 Mbps | 100 Mbps |
| Output Architecture | Transmission-gate with weak bus keepers | Push-pull driver stage | Transmission-gate with weak bus keepers |
| OE / 3-State | Yes (OE pin) | Yes (OE pin) | Yes (OE pin) |
关键差异点
- Auto direction sensing with no DIR pin （对比 NTS0102GT,115)
- Stronger drive for capacitive loads （对比 NTS0102GT,115)
- Extended temperature variant available in same footprint （对比 NTB0102GT,125)
设计说明
The NTB0102 uses weak pull-up bus keepers, so translated lines must be actively driven push-pull on at least one side, or fitted with external pull-up resistors sized for the bus speed. Keep traces under ~10 cm where possible and minimize stub capacitance; the effective bandwidth degrades with load, and the 100 Mbps rating assumes light loading. For open-drain I2C, set pull-ups so rise time meets the target speed class - typically 1 kOhm to 4.7 kOhm depending on bus capacitance and rail voltage.
Power VCC(A) and VCC(B) from the respective domain rails, not from a shared regulator, so the Ioff partial power-down feature works: if one supply collapses, the device will not back-drive the dead rail through the translation cells. Use 100 nF ceramic decoupling on both VCC pins placed within 2 mm of the package. During bring-up, hold OE low until both rails are stable to prevent undefined levels or contention; a resistor pull-up on OE to VCC(A) gives a defined default-enabled state.
The SOT833-1 XSON-8 outline is only 1.95 x 1 mm with 0.35 mm pitch lands - follow the NXP footprint and reflow profile recommendations in the data sheet, as hand rework at this pitch is difficult. Verify pin-1 marking orientation under magnification; the package is small enough that rotation errors are common on prototypes. Place the translator physically between the two voltage domains to keep both sides' trace stubs short and route A-side and B-side nets on their own domain reference planes to control return paths.
Do not use the NTB0102 on heavily loaded multidrop buses without external pull-ups - the weak keepers cannot hold a level against residual capacitance discharge, which appears as floating glitches. Do not exceed 3.6 V on either supply; there is no 5 V-tolerant input on either port. If higher drive strength is needed later, the pin-compatible NTS0102GT,115 push-pull variant can be substituted without a PCB change - validate edges and overshoot after substitution.
合规信息
RoHS-compliant termination implied by NXP ,115 ordering code per manufacturer product page and distributor listings. Obtain REACH and conflict-minerals declarations directly from NXP.
