SI5341B-B05471-GM - 10-Output Ultra-Low-Jitter Clock Generator | Skyworks
料号： SI5341B-B05471-GM ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $22.5 | $22.50 |
| 10 | $20.95 | $209.50 |
| 100 | $19.1 | $1,910.00 |
| 500 | $17.85 | $8,925.00 |
| 1,000 | $16.89 | $16,890.00 |
SI5341B-B05471-GM 概述
A clock generator is a semiconductor device that produces one or more precisely timed reference signals used to synchronize digital logic, converters, serializers, and RF front-ends. Within the broader hierarchy, the SI5341B-B05471-GM is a PLL-based frequency synthesizer that belongs to the clock generator family, itself a sub-category of clock & timing ICs in the power management / signal chain ecosystem. Unlike simple crystal oscillators, multi-output clock generators like the Si5341B consolidate what would otherwise require multiple discrete XOs and fanout buffers into a single IC configurable via I2C/SPI, simplifying BOM and improving timing margin across PCB regions.
Key features include 0.09 ps RMS phase jitter, 4 reference inputs (differential or single-ended), 10 output drivers (selectable LVDS/LVPECL/HCSL/CMOS), an on-chip fractional-N PLL with MultiSynth technology, and a per-output integer divider. The device supports output frequencies from < 1 Hz up to 350 MHz on any output, with independent frequency and format programming. The integrated XTAL oscillator accepts a 25 MHz to 54 MHz fundamental-mode resonator for smooth frequency and format programming.
The Si5341B architecture combines a low-noise MultiSynth fractional divider stage with a high-frequency VCO, achieving jitter performance that previously required discrete VCXOs plus custom ASICs. ClockBuilder Pro software generates the register map that initializes the device, removing manual I2C programming and reducing firmware development time.
Typical applications include 100G/400G optical transport, OTN/SONET/SDH line cards, broadcast video reference timing, wireless baseband and digital front-end (DFE) clocking, enterprise switch/router timing, and FPGA/ASIC reference clock distribution. Any application requiring multiple low-jitter, format-flexible clocks from a single reference benefits from the Si5341B.
When designing with this part, use the ClockBuilder Pro GUI to generate the device profile - register map, frequency plan, and pin configuration - and avoid manual programming. Layout must follow Skyworks application note AN862 (jitter optimization) to minimize output-to-output crosstalk and power-supply noise coupling.
This page aggregates Skyworks-published specs, distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone - giving a holistic view for BOM decisions.
直接替换替代料： SI5341B-B05471-GM ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： SI5341B-B05471-GM （相同外形与封装尺寸） ——差异在于 Maximum Output Frequency, Number of Outputs, Number of Reference Inputs, Package.
快速对比工具——选择替代料号进行并排对比：
SI5341B-B05471-GMR
✅ 直接替换📋 参考替代料（不在目录中）
SI5341B-D-GM
✅ 直接替换📋 参考替代料（不在目录中）
SI5341B-B05071-GM
✅ 直接替换📋 参考替代料（不在目录中）
SI5341B-B05049-GM
✅ 直接替换📋 参考替代料（不在目录中）
SI5340A-B05364-GM
✅ 直接替换✓ 有现货
$9.85 / 个
查看数据手册 →SI5341B-B05471-GM 规格参数
| 功能 | Clock generator, PLL, frequency synthesizer |
| 输出数量 | 10 |
| Maximum Output Frequency | 350 MHz |
| Phase Jitter (RMS) | 0.09 ps typical (12 kHz to 20 MHz) |
| Number of Reference Inputs | 4 (differential or single-ended) |
| Frequency Synthesis Modes | Integer-N and Fractional-N |
| Output Formats | LVDS, LVPECL, HCSL, CMOS (programmable per output) |
| Reference Frequency | 25 MHz to 54 MHz fundamental-mode XTAL |
| Control Interface | I2C / SPI |
| Configuration Tool | ClockBuilder Pro |
| 封装 | 64-VFQFN Exposed Pad (Tray) |
| MSL 等级 | 2 (1 year floor life) |
| ECCN | EAR99 |
| HTSUS | 8542.39.0001 |
| 工作温度 | -40C to +85C (industrial) |
| 安装类型 | Surface Mount |
SI5341B-B05471-GM 引脚配置
| 引脚 1 | VDD — Core supply voltage |
| 引脚 2 | IN0 — Reference input 0 (differential or single-ended) |
| 引脚 3 | IN0b — Reference input 0 complement |
| 引脚 4 | VDD — Core supply voltage |
| 引脚 5 | IN1 — Reference input 1 |
| 引脚 6 | IN1b — Reference input 1 complement |
| 引脚 7 | VDD — Core supply voltage |
| 引脚 8 | IN2 — Reference input 2 |
| 引脚 9 | IN2b — Reference input 2 complement |
| 引脚 10 | VDD — Core supply voltage |
| 引脚 11 | IN3 — Reference input 3 |
| 引脚 12 | IN3b — Reference input 3 complement |
| 引脚 13 | VDD — Core supply voltage |
| 引脚 14 | XA — Crystal oscillator input |
| 引脚 15 | XB — Crystal oscillator input |
| 引脚 16 | VDD — Core supply voltage |
| 引脚 17 | SDA — I2C serial data |
| 引脚 18 | SCL — I2C serial clock |
| 引脚 19 | CSb — SPI chip select (active low) |
| 引脚 20 | SCLK — SPI serial clock |
| 引脚 21 | SDIO — SPI serial data input/output |
| 引脚 22 | VDD — I/O supply voltage |
| 引脚 23 | A0 — I2C address select 0 |
| 引脚 24 | A1 — I2C address select 1 |
| 引脚 25 | VDD — I/O supply voltage |
| 引脚 26 | OUT0 — Clock output 0 |
| 引脚 27 | OUT0b — Clock output 0 complement |
| 引脚 28 | VDD — Output driver supply |
| 引脚 29 | OUT1 — Clock output 1 |
| 引脚 30 | OUT1b — Clock output 1 complement |
| 引脚 31 | VDD — Output driver supply |
| 引脚 32 | OUT2 — Clock output 2 |
| 引脚 33 | OUT2b — Clock output 2 complement |
| 引脚 34 | VDD — Output driver supply |
| 引脚 35 | OUT3 — Clock output 3 |
| 引脚 36 | OUT3b — Clock output 3 complement |
| 引脚 37 | VDD — Output driver supply |
| 引脚 38 | OUT4 — Clock output 4 |
| 引脚 39 | OUT4b — Clock output 4 complement |
| 引脚 40 | VDD — Output driver supply |
| 引脚 41 | OUT5 — Clock output 5 |
| 引脚 42 | OUT5b — Clock output 5 complement |
| 引脚 43 | VDD — Output driver supply |
| 引脚 44 | OUT6 — Clock output 6 |
| 引脚 45 | OUT6b — Clock output 6 complement |
| 引脚 46 | VDD — Output driver supply |
| 引脚 47 | OUT7 — Clock output 7 |
| 引脚 48 | OUT7b — Clock output 7 complement |
| 引脚 49 | VDD — Output driver supply |
| 引脚 50 | OUT8 — Clock output 8 |
| 引脚 51 | OUT8b — Clock output 8 complement |
| 引脚 52 | VDD — Output driver supply |
| 引脚 53 | OUT9 — Clock output 9 |
| 引脚 54 | OUT9b — Clock output 9 complement |
| 引脚 55 | VDD — Output driver supply |
| 引脚 56 | GND — Ground |
| 引脚 57 | RESETb — Reset (active low) |
| 引脚 58 | IRQ — Interrupt request output |
| 引脚 59 | OEb — Output enable (active low, common) |
| 引脚 60 | STATUS0 — Loss-of-lock / status output 0 |
| 引脚 61 | STATUS1 — Status output 1 |
| 引脚 62 | GND — Ground |
| 引脚 63 | GND — Ground (e-pad bond recommended) |
| 引脚 64 | EPAD — Exposed thermal pad - must be soldered to PCB ground |
典型应用
SI5341B-B05471-GM 适用于 6 应用s: 100G/400G Optical Transport Reference Clocking, Wireless Base Station Baseband Clocking, Broadcast Video Reference Timing (SMPTE), Enterprise Switch / Router Timing, Test & Measurement Instrumentation, FPGA / ASIC Reference Clock Distribution.
100G/400G Optical Transport Reference Clocking
The SI5341B-B05471-GM provides the multiple low-jitter reference clocks required by 100G and 400G optical transceiver modules (CFP2, QSFP-DD, OSFP). With 0.09 ps RMS phase jitter, the device easily meets the IEEE 802.3bs and OIF-CEI-25G reference clock jitter masks for 25.78125 Gbd and 53.125 Gbd SerDes. The 10 outputs allow simultaneous generation of the host-side refclk, line-side refclk, and module-side management clock from a single 156.25 MHz or 161.13 MHz input.
推荐
Wireless Base Station Baseband Clocking
In 4G/5G base stations, the SI5341B-B05471-GM generates the multi-rate clocks required by CPRI/eCPRI links, FPGA baseband processors, and ADC/DAC sample clocks. The 0.09 ps jitter keeps EVM within 3GPP TS 36.104 limits for LTE and 5G NR FR1. The 4-reference-input architecture supports hitless switching between GPS-disciplined OCXO and the baseband card local reference - a critical feature for carrier-grade synchronization (G.8275.1).
推荐
Broadcast Video Reference Timing (SMPTE)
The SI5341B-B05471-GM is widely used in broadcast video routers and reference generators for SMPTE ST 2059-2 (PTP) and ST 424 (3G-SDI) timing distribution. Its fractional-N MultiSynth technology provides the 1 Hz resolution needed to generate video reference rates (27 MHz, 74.25 MHz, 148.5 MHz) without the need for multiple discrete XOs. The 10 outputs feed SDI cards, PTP grandmaster clocks, and audio embedder modules from a single timing source.
推荐
Enterprise Switch / Router Timing
Enterprise-class L2/L3 switches and routers with 25G/50G/100G uplinks require multiple synchronized clocks for SerDes, PHY, MAC, and management processors. The SI5341B-B05471-GM provides the 156.25 MHz and 312.5 MHz reference clocks needed by QSFP28 optics and 25G Ethernet PHYs, plus auxiliary clocks for the management CPU and switching ASIC. Its low jitter preserves the link margin required by IEEE 802.3bj and 802.3cd specifications.
推荐
Test & Measurement Instrumentation
High-end oscilloscopes, BERTs, and signal analyzers require an internal reference clock tree that can drive ADCs, DACs, and FPGA signal-processing fabric at low jitter. The SI5341B-B05471-GM provides 10 independently programmable outputs that generate ADC sample clocks, FPGA fabric clocks, and display processor clocks from a single 10 MHz laboratory reference. ClockBuilder Pro lets the test engineer reconfigure the frequency plan without external XO swaps.
推荐
FPGA / ASIC Reference Clock Distribution
In FPGA prototyping boards and ASIC reference designs, the SI5341B-B05471-GM distributes the multiple clock domains required by transceivers (GTX/GTY/GTH), fabric logic, and DDR memory controllers. The independent output frequency programming lets designers feed each FPGA bank with its optimal clock (e.g., 156.25 MHz for transceivers, 200 MHz for fabric, 300 MHz for DDR4) while sharing one XTAL reference - saving board area and BOM cost.
推荐
推荐产品汇总
工程参考数据： SI5341B-B05471-GM ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | SI5341B-B05471-GMR | SI5341B-D-GM | SI5341B-B05071-GM | SI5341B-B05049-GM | SI5340A-B05364-GM |
|---|---|---|---|---|---|---|
| Package | 64-VFQFN Exposed Pad | 64-VFQFN Exposed Pad - same | 64-VFQFN Exposed Pad - same | 64-VFQFN Exposed Pad - same | 64-VFQFN Exposed Pad - same | 64-VFQFN Exposed Pad - same |
| Brand | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions |
| Number of Outputs | 10 | 10 | 10 | 10 | 10 | 4 |
| Maximum Output Frequency | 350 MHz | 350 MHz | 350 MHz | 350 MHz | 350 MHz | 350 MHz |
| Phase Jitter (RMS) | 0.09 ps | 0.09 ps | 0.09 ps | 0.09 ps | 0.09 ps | 0.1 ps (slightly higher) |
| Number of Reference Inputs | 4 | 4 | 4 | 4 | 4 | 2 |
| Frequency Synthesis | Integer + Fractional-N | Integer + Fractional-N | Integer + Fractional-N | Integer + Fractional-N | Integer + Fractional-N | Integer + Fractional-N |
| Factory Frequency Plan | B05471 (100G optical) | B05471 (same as this product) | D (broadcast video) | B05071 (100G Ethernet refclk) | B05049 (wireless baseband) | B05364 (4-output) |
| Packaging | Tray | Tape & Reel | Tray | Tray | Tray | Tray |
关键差异点
- 10 independent outputs vs 4-output Si5340A sibling （对比 SI5340A-B05364-GM)
- 4 reference inputs vs 2 in lower-end clock generators （对比 SI5340A-B05364-GM)
- Pre-programmed factory profile eliminates firmware development （对比 SI5341B-D-GM)
- ClockBuilder Pro configuration vs manual register programming （对比 Generic clock generators without GUI tools)
设计说明
Estimated: The 64-VFQFN exposed pad must be soldered to a continuous PCB ground plane with at least 8 thermal vias (0.3 mm drill, 0.6 mm pitch) to provide both thermal dissipation (theta_JA < 25 C/W with proper ground pour) and low-impedance ground reference for the PLL. Star-ground the analog VDD (XA/XB supply) separately from the digital VDD - place 1uF and 0.1uF ceramic bypass caps within 1 mm of every VDD pin. Skyworks application note AN862 recommends keeping output trace lengths < 5 cm and 50 ohm controlled impedance.
Each of the 10 differential outputs should have its own ground-shielded 100-ohm differential trace pair - DO NOT share ground return paths between outputs as this couples jitter between channels. Place the Si5341B on a layer adjacent to the main ground plane with continuous ground beneath. LVDS and LVPECL outputs require 100 ohm differential termination at the receiver; CMOS outputs require series 33 ohm at the driver pin to dampen reflections. Reference AN862 section 4 for the reference layout of a 10-output design.
Avoid routing LVDS/LVPECL outputs parallel to each other on adjacent layers - use orthogonal crossings or guard traces tied to ground to minimize crosstalk. The fractional-N MultiSynth can produce sub-Hz output resolution, but output-to-output crosstalk at 156.25 MHz with multiple outputs simultaneously active can add 50-150 fs of jitter if layout is poor. Skyworks datasheet section 8 specifies the jitter measurement methodology (12 kHz to 20 MHz integration) used to qualify the 0.09 ps spec - any deviation from the reference layout can degrade real-world jitter.
Common pitfall #1: using a non-ClockBuilder-Pro configuration method. Do not attempt manual I2C register programming - the Si5341B has >300 configuration registers and an error in pre-divider or post-divider selection can produce fractional spurs or loss-of-lock. Always generate the register map in ClockBuilder Pro. Pitfall #2: omitting the reset sequence - the Si5341B must see RESETb held low for at least 1 ms after VDD is stable, otherwise the device may power up in an undefined state with no outputs. Pitfall #3: driving the XA/XB crystal pins with an external clock reference before the Si5341B has been configured, which can confuse the internal PLL state machine.
Estimated: The Si5341B draws approximately 250 mA per VDD rail when all 10 outputs are active with LVDS swing. Total power dissipation is around 1.5 W at typical supply voltages, requiring 1 square inch of 2-oz copper pour on the exposed pad to keep junction below 125 C at 85 C ambient. Use ferrite beads to isolate digital VDD noise from the analog VDD that powers the PLL VCO - Skyworks recommends a 600 ohm ferrite at 100 MHz (Murata BLM18AG601SN1 or equivalent). Add 22uF tantalum bulk capacitors near the supply pins in addition to the 1uF/0.1uF ceramic bypass.
合规信息
RoHS and REACH compliant per Skyworks product page. Not AEC-Q100 qualified - industrial temperature grade only. For automotive applications, contact Skyworks for AEC-Q100 qualified variant availability. ECCN EAR99 - no export license required. HTSUS 8542.39.0001 (clock generator ICs).
