SI5341B-D08976-GM - 10-Output Ultra-Low Jitter Clock Generator | Skyworks
料号： SI5341B-D08976-GM ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $22.5 | $22.50 |
| 10 | $20.25 | $202.50 |
| 100 | $17.8 | $1,780.00 |
| 500 | $15.4 | $7,700.00 |
| 1,000 | $13.95 | $13,950.00 |
SI5341B-D08976-GM 概述
What is a clock generator? A clock generator is a timing integrated circuit that synthesizes one or more output clock signals from one or more reference inputs (crystal, LVCMOS, or differential clock). Clock generators belong to the clock and timing IC family within the broader power management and signal chain hierarchy, and they are foundational building blocks in nearly every digital system. The SI5341B family specifically targets ultra-low jitter applications such as 100G/400G optical modules, broadband communications, and high-speed data converters, where phase noise directly limits bit-error-rate and signal-to-noise ratio.
The SI5341B supports input frequency ranges of 25 to 54 MHz from an external crystal, 10 to 750 MHz from a differential clock, and 10 to 250 MHz from an LVCMOS clock. It provides both integer and fractional frequency synthesis modes, four reference inputs, and 10 configurable outputs. Phase jitter is rated at 0.09 ps RMS, a figure that places it among the lowest-jitter clock generators in its class and enables compliance with the most stringent telecom and datacom standards such as OTU/STM-64, PCIe Gen 5, and 56G/112G SerDes reference clock requirements.
Architecturally, the SI5341B integrates a MultiSynth fractional divider engine, a low-noise PLL with integrated VCO, and per-output divider and driver stages. The device is configured through I2C/SPI with a graphical ClockBuilder Pro software tool that simplifies register programming. Outputs can be independently configured as LVDS, LVPECL, HCSL, CML, or LVCMOS, allowing direct connection to serializers, FPGAs, ASICs, and DACs without external level translation.
Typical applications include wired networking (switches, routers, line cards), optical transport (OTN/SONET/SDH), wireless base stations, broadcast video, test and measurement equipment, and high-performance FPGA/ASIC reference clock trees. In each of these, the SI5341B replaces multiple fixed-frequency oscillators and PLL devices with a single programmable part, simplifying BOM and improving frequency agility across product variants.
When designing with the SI5341B, ensure the exposed pad is soldered to a sufficient ground plane for thermal dissipation and noise isolation. Place decoupling capacitors as close as possible to the supply pins and follow Skyworks application note AN862 for jitter optimization in next-generation internet infrastructure systems. Output format, drive strength, and frequency for each of the 10 outputs should be configured via ClockBuilder Pro before register loading.
This page synthesizes distributor pricing, drop-in alternatives within the Si534x family, and practical design notes not found in the manufacturer datasheet summary, providing engineers with a single-source reference for evaluation and procurement decisions.
直接替换替代料： SI5341B-D08976-GM ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： SI5341B-D08976-GM （相同外形与封装尺寸） ——差异在于 Package, Number of Outputs, Product Type, Operating Temperature Range, Output Formats.
快速对比工具——选择替代料号进行并排对比：
SI5341B-D-GM
✅ 直接替换📋 参考替代料（不在目录中）
SI5341B-D08976-GMR
✅ 直接替换📋 参考替代料（不在目录中）
SI5341A-D07228-GM
✅ 直接替换✓ 有现货
$18.92 / 个
查看数据手册 →SI5341B-D07870-GMR
✅ 直接替换✓ 有现货
$10.85 / 个
查看数据手册 →SI5340A-D-GM
✅ 直接替换✓ 有现货
$14.75 / 个
查看数据手册 →SI5340A-B05364-GM
✅ 直接替换✓ 有现货
$9.85 / 个
查看数据手册 →SI5341B-D08976-GM 规格参数
| Product Type | Clock Generator, Any-Frequency, Any-Output |
| 输出数量 | 10 |
| Maximum Output Frequency | 350 MHz |
| Input Frequency Range (Crystal) | 25 MHz to 54 MHz |
| Input Frequency Range (Differential) | 10 MHz to 750 MHz |
| Input Frequency Range (LVCMOS) | 10 MHz to 250 MHz |
| Phase Jitter (RMS) | 0.09 ps (typical) |
| Output Jitter | 90 fs RMS (typical, 12 kHz to 20 MHz) |
| Number of Reference Inputs | 4 |
| Synthesis Modes | Integer and Fractional |
| Output Formats | LVDS, LVPECL, HCSL, CML, LVCMOS |
| Control Interface | I2C / SPI |
| 封装 | 64-pin VFQFN Exposed Pad (9x9 mm) |
| Operating Temperature Grade | Industrial |
| Configuration Tool | ClockBuilder Pro |
| RoHS 状态 | Compliant |
SI5341B-D08976-GM 引脚配置
| 引脚 1 | IN0 — Reference clock input 0 (differential pair with IN0b) |
| 引脚 2 | IN0b — Complementary reference clock input 0 |
| 引脚 3 | VDD — Core supply voltage |
| 引脚 4 | IN1 — Reference clock input 1 (differential pair with IN1b) |
| 引脚 5 | IN1b — Complementary reference clock input 1 |
| 引脚 6 | GND — Ground |
| 引脚 7 | IN2 — Reference clock input 2 (LVCMOS) |
| 引脚 8 | VDD — Core supply voltage |
| 引脚 9 | IN3 — Reference clock input 3 (LVCMOS) |
| 引脚 10 | GND — Ground |
| 引脚 11 | XIN — Crystal oscillator input |
| 引脚 12 | XOUT — Crystal oscillator output |
| 引脚 13 | VDD — Core supply voltage |
| 引脚 14 | GND — Ground |
| 引脚 15 | SDA/SDI — I2C data / SPI serial data input |
| 引脚 16 | SCL/SCLK — I2C clock / SPI serial clock |
| 引脚 17 | A0/CS — I2C address select / SPI chip select |
| 引脚 18 | A1 — I2C address select |
| 引脚 19 | INT — Interrupt output (open-drain, active-low) |
| 引脚 20 | RSTb — Reset input (active-low) |
| 引脚 21 | GND — Ground |
| 引脚 22 | OUT0 — Clock output 0 (differential pair with OUT0b) |
| 引脚 23 | OUT0b — Complementary clock output 0 |
| 引脚 24 | VDD — Output driver supply |
| 引脚 25 | OUT1 — Clock output 1 (differential pair with OUT1b) |
| 引脚 26 | OUT1b — Complementary clock output 1 |
| 引脚 27 | GND — Ground |
| 引脚 28 | OUT2 — Clock output 2 |
| 引脚 29 | OUT2b — Complementary clock output 2 |
| 引脚 30 | VDD — Output driver supply |
| 引脚 31 | OUT3 — Clock output 3 |
| 引脚 32 | OUT3b — Complementary clock output 3 |
| 引脚 33 | GND — Ground |
| 引脚 34 | OUT4 — Clock output 4 |
| 引脚 35 | OUT4b — Complementary clock output 4 |
| 引脚 36 | VDD — Output driver supply |
| 引脚 37 | OUT5 — Clock output 5 |
| 引脚 38 | OUT5b — Complementary clock output 5 |
| 引脚 39 | GND — Ground |
| 引脚 40 | OUT6 — Clock output 6 |
| 引脚 41 | OUT6b — Complementary clock output 6 |
| 引脚 42 | VDD — Output driver supply |
| 引脚 43 | OUT7 — Clock output 7 |
| 引脚 44 | OUT7b — Complementary clock output 7 |
| 引脚 45 | GND — Ground |
| 引脚 46 | OUT8 — Clock output 8 |
| 引脚 47 | OUT8b — Complementary clock output 8 |
| 引脚 48 | VDD — Output driver supply |
| 引脚 49 | OUT9 — Clock output 9 |
| 引脚 50 | OUT9b — Complementary clock output 9 |
| 引脚 51 | GND — Ground |
| 引脚 52 | VDD — Output driver supply |
| 引脚 53 | NC — Not connected (per datasheet) |
| 引脚 54 | NC — Not connected (per datasheet) |
| 引脚 55 | NC — Not connected (per datasheet) |
| 引脚 56 | GND — Ground |
| 引脚 57 | NC — Not connected (per datasheet) |
| 引脚 58 | NC — Not connected (per datasheet) |
| 引脚 59 | NC — Not connected (per datasheet) |
| 引脚 60 | NC — Not connected (per datasheet) |
| 引脚 61 | NC — Not connected (per datasheet) |
| 引脚 62 | NC — Not connected (per datasheet) |
| 引脚 63 | NC — Not connected (per datasheet) |
| 引脚 64 | GND — Ground |
典型应用
SI5341B-D08976-GM 适用于 6 应用s: 100G/400G Optical Transport Clocking, Wireless Base Station Timing, High-Speed Data Converter Clocking, FPGA/ASIC Reference Clock Tree, Broadcast Video and Professional Audio, Industrial Automation and Control.
100G/400G Optical Transport Clocking
The SI5341B-D08976-GM is well-suited as the reference clock generator for 100G/400G coherent optical modules where its 0.09 ps RMS phase jitter and 90 fs RMS output jitter directly enable OTU/STM-64 compliance. With 10 independent outputs, a single device can drive the modulator driver, DAC, ADC, and forward-error-correction ASIC simultaneously, replacing multiple XO/PLL chains. The 64-pin VQFN exposed pad simplifies layout under the optical cage, and ClockBuilder Pro allows fast customization across CFP2, QSFP-DD, and OSFP module variants. Designers should follow Skyworks AN862 for optimal jitter performance in next-generation internet infrastructure systems.
推荐
Wireless Base Station Timing
In 4G LTE and 5G NR base stations, the SI5341B-D08976-GM provides the low-jitter reference clocks required by radio units, baseband processors, and fronthaul CPRI/eCPRI links. Its 350 MHz maximum output frequency and configurable LVDS/LVPECL/HCSL drive formats support direct connection to radios and SerDes without level translation. The fractional synthesis mode enables non-integer frequency relationships between radio channels and baseband DSP clocks, eliminating the need for multiple crystal oscillators. Industrial temperature grade ensures operation in outdoor base-station enclosures.
推荐
High-Speed Data Converter Clocking
The SI5341B-D08976-GM drives high-speed ADC and DAC sampling clocks in test-and-measurement, radar, and broadband communications equipment. Its 0.09 ps RMS phase jitter is well below the aperture-jitter requirement of most 12- to 16-bit GSPS converters, preserving signal-to-noise ratio at the converter output. The 10 outputs allow parallel sampling of multiple ADC channels with matched phase, critical for I/Q demodulation and beamforming applications. Per-output skew control and LVDS/HCPECL formats simplify board layout.
推荐
FPGA/ASIC Reference Clock Tree
FPGAs and ASICs in networking switches, routers, and high-performance compute platforms require multiple low-jitter reference clocks for SerDes, transceivers, and fabric logic. The SI5341B-D08976-GM provides 10 independent clocks from a single reference, replacing multiple XO/PLL devices and simplifying the BOM. Its I2C/SPI control interface allows the host processor to dynamically reconfigure frequencies during system operation, supporting line-card rate changes and multi-rate SerDes. ClockBuilder Pro generates complete register initialization scripts for common FPGA/ASIC reference clock trees.
推荐
Broadcast Video and Professional Audio
The SI5341B-D08976-GM provides low-jitter clocks for broadcast video routers, SDI/HDMI processing, and professional audio sample-clock distribution. Its fractional synthesis mode generates the precise 27 MHz, 74.25 MHz, 148.5 MHz, and 297 MHz reference frequencies required for SD-SDI, HD-SDI, 3G-SDI, 12G-SDI, and UltraHD video formats from a single 10 MHz or 25 MHz master reference. The LVDS/HCSL output formats drive most video PHYs directly, and the 0.09 ps RMS jitter specification exceeds SMPTE 2059 jitter tolerance requirements.
推荐
Industrial Automation and Control
In programmable logic controllers (PLCs), industrial Ethernet switches, and motor-control systems, the SI5341B-D08976-GM provides deterministic multi-clock-domain timing. Industrial temperature grade (-40 to +85 C), long-term reliability, and I2C/SPI dynamic reconfiguration make it a fit for factory-automation controllers requiring flexible EtherCAT, PROFINET, or EtherNet/IP reference clocking. The 10 outputs serve the host CPU, FPGA fabric, Ethernet PHYs, and ADC sample clocks from a single part, reducing BOM and improving MTBF in always-on industrial deployments.
推荐
推荐产品汇总
工程参考数据： SI5341B-D08976-GM ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | SI5341B-D-GM | SI5341B-D08976-GMR | SI5341A-D07228-GM | SI5341B-D07870-GMR | SI5340A-D-GM | SI5340A-B05364-GM |
|---|---|---|---|---|---|---|---|
| Brand | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks |
| Package | 64-pin VFQFN EP (9x9 mm) | 64-pin VFQFN EP (9x9 mm) - same | 64-pin VFQFN EP (9x9 mm) - same | 64-pin VFQFN EP (9x9 mm) - same | 64-pin VFQFN EP (9x9 mm) - same | 64-pin VFQFN EP (9x9 mm) - same | 64-pin VFQFN EP (9x9 mm) - same |
| Number of Outputs | 10 | 10 | 10 | 10 | 10 | 4 (-60%) | 4 (-60%) |
| Maximum Output Frequency | 350 MHz | 350 MHz | 350 MHz | 350 MHz | 350 MHz | 350 MHz | 350 MHz |
| Factory Frequency Plan | Yes (-D08976- code) | No (customer programmed) | Yes (-D08976- code, T&R) | Yes (-D07228- code) | Yes (-D07870- code, T&R) | No (customer programmed) | Yes (-B05364- code) |
| Packaging | Tray (GM suffix) | Tray (GM suffix) | Tape & Reel (GMR suffix) | Tray (GM suffix) | Tape & Reel (GMR suffix) | Tray (GM suffix) | Tray (GM suffix) |
| Synthesis Modes | Integer + Fractional | Integer + Fractional | Integer + Fractional | Integer + Fractional | Integer + Fractional | Integer + Fractional | Integer + Fractional |
| Reference Inputs | 4 | 4 | 4 | 4 | 4 | 4 | 4 |
| Configuration Tool | ClockBuilder Pro | ClockBuilder Pro | ClockBuilder Pro | ClockBuilder Pro | ClockBuilder Pro | ClockBuilder Pro | ClockBuilder Pro |
关键差异点
- 10 outputs in a single 64-pin VQFN package （对比 SI5340A-D-GM)
- Factory-programmed frequency plan (-D08976- code) （对比 SI5341B-D-GM)
- 0.09 ps RMS phase jitter exceeds most telecom/SerDes requirements （对比 SI5341A-D07228-GM)
设计说明
The 64-pin VFQFN exposed pad is the primary thermal dissipation path and MUST be soldered to a continuous ground plane with at least 16 thermal vias (0.3 mm drill, 0.5 mm pitch) connecting to inner ground layers. Place 100 nF X7R 0402 ceramic decoupling capacitors within 2 mm of every VDD pin and a single 10 uF X5R bulk capacitor adjacent to the supply rail. Route differential output pairs (OUTx/OUTxb) as 100 ohm differential impedance with matched lengths (skew <5 mils) and keep them isolated from switching signals with a continuous ground-side reference plane.
Common pitfalls when designing with the SI5341B-D08976-GM include: (1) using the GMR (Tape-and-Reel) part number on hand-assembled prototypes when only the GM (tray) variant is suitable for lab work; (2) assuming the -D08976- factory plan is interchangeable with another Si5341B plan - it is NOT, you must use the exact plan for functional drop-in; (3) forgetting to ground the exposed pad, which causes thermal shutdown at moderate output loading; (4) routing I2C/SPI traces >50 mm without pull-up resistors or buffered repeaters, which can cause bus lockup; (5) using CMOS outputs adjacent to differential outputs, which causes crosstalk - see Skyworks AN862 for jitter optimization guidance.
For 100G/400G optical module applications, route each clock output pair through a 100 ohm differential transmission line with via count minimized (use 2 vias per pair maximum). Keep CMOS outputs isolated from low-jitter differential pairs by at least 4x the trace width. If multiple Si5341B devices share a board, separate their power islands with ferrite beads to prevent reference spurs from coupling between PLLs. Estimated: with 10 LVDS outputs at 156.25 MHz and 50 ohm terminations, each output consumes ~25 mA of bias current plus AC load - total device power ~1 W under typical loading.
合规信息
RoHS and REACH compliance per Skyworks product page. Industrial temperature grade. Not AEC-Q100 qualified (clock generators typically are not AEC-Q100 parts).
