Si5366 - 1.05GHz Jitter-Attenuating Clock Multiplier | Skyworks
料号： Si5366 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $18.9 | $18.90 |
| 10 | $17.5 | $175.00 |
| 100 | $15.95 | $1,595.00 |
| 500 | $14.6 | $7,300.00 |
| 1,000 | $13.75 | $13,750.00 |
Si5366 概述
A jitter attenuator is a specialized clock IC that cleans reference clocks by phase-locking a low-noise oscillator to a noisy input and filtering the timing jitter inside a narrow bandwidth. Within the clock-management hierarchy (clock generator -> clock multiplier -> jitter attenuator -> timing IC -> signal integrity chain), the Si5366 sits at the critical point where an unstable recovered or reference clock must be converted into a standards-compliant, low-jitter output for high-speed serializers and framer devices.
Key features include any-frequency input and output capability across the 8 kHz to 1050 MHz span, DSPLL-based jitter cleaning with selectable bandwidth, support for SONET OC-48/OC-192, 10 Gigabit Ethernet, and Fibre Channel rates, and four independent inputs with automatic or manual failover for redundant clocking. According to the Skyworks datasheet, the device integrates the loop filter and VCO, minimizing external components and board area.
The third-generation DSPLL architecture replaces a conventional analog PLL with a digital loop that achieves very low jitter generation and tight output-to-input phase tracking, enabling designs to pass stringent standards such as GR-253 and IEEE 802.3 jitter masks without discrete crystal filtering.
Typical applications include SONET/SDH line-card reference clocks at 155.52 MHz, 622.08 MHz, and 2.48 GHz derived rates, 10GbE and Fibre Channel transceiver reference cleaning, and central-office synchronization (BITS/SSU) distribution.
Design consideration: supply noise directly modulates the VCO, so use dedicated low-noise LDO supplies and solid ground planes; jitter floor degrades quickly with noisy 3.3 V rails.
This page synthesizes distributor pricing, drop-in family alternatives, and practical design notes not found in the manufacturer datasheet.
直接替换替代料： Si5366 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： Si5366 （相同外形与封装尺寸） ——差异在于 Core Technology, Input Frequency Range, Jitter Attenuation, Loop Filter, Output Frequency Range.
快速对比工具——选择替代料号进行并排对比：
Si5365-C-GQ
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
Si5367-C-GQ
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
Si5368-C-GQ
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
Si5319-C-GM
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
Si5366 规格参数
| 功能 | Jitter-attenuating precision clock multiplier |
| Number of Clock Inputs | 4 |
| Input Frequency Range | 8 kHz to 707 MHz |
| Number of Clock Outputs | 5 |
| Output Frequency Range | 8 kHz to 1050 MHz |
| PLL Technology | 3rd-generation DSPLL |
| Max Output Frequency | 1.05 GHz |
| Target Standards | SONET OC-48/OC-192, Ethernet, Fibre Channel |
| Input Redundancy | 4 inputs with automatic/manual failover |
| 封装 | 100-TQFP |
| 安装类型 | Surface Mount |
| Loop Filter | Integrated (DSPLL, no external loop filter) |
| RoHS 状态 | Compliant |
Si5366 100-tqfp 引脚配置指南
Si5366（100-tqfp 封装）的引脚配置。 引脚编号、功能和连接图在制造商数据手册中定义。请参阅该手册以了解确切的封装尺寸和焊接指南。
暂无详细引脚数据： Si5366.
请参阅 数据手册 以查看完整引脚配置。
典型应用
Si5366 适用于 6 应用s: SONET/SDH OC-48/OC-192 Line Cards, 10 Gigabit Ethernet Switch and Router Timing, Fibre Channel SAN Switch Clock Generation, Central Office BITS/SSU Synchronization Distribution, Optical Transport Network (OTN) Transponder Timing, Test and Measurement Instrument Clock Subsystem.
SONET/SDH OC-48/OC-192 Line Cards
The Si5366 is explicitly designed for SONET OC-48 and OC-192 systems, per the Skyworks datasheet, making it the natural jitter-cleaning element on optical transport line cards. A recovered clock from the CDR carries transport jitter that would violate downstream serializer jitter tolerances; the Si5366 accepts that noisy 622.08 MHz or 155.52 MHz reference (within its 8 kHz to 707 MHz input range) and regenerates it with the narrow-band DSPLL, attenuating wideband jitter while multiplying to the required serializer reference. With four inputs, one device handles both working and protection BITS references plus local oscillator backup with automatic hitless failover, and its five outputs fan out to the framer, mapper, and line-side PHYs. The integrated loop filter eliminates external RC tuning, keeping jitter-transfer characteristics stable over temperature and unit-to-unit variation.
推荐
10 Gigabit Ethernet Switch and Router Timing
10GbE line interfaces require reference clocks with jitter well below the IEEE 802.3 masks, and backplane-distributed references often arrive degraded after crossing connectors and fanout buffers. The Si5366's 8 kHz to 707 MHz input range accepts standard 156.25 MHz or 312.5 MHz backplane references, and its DSPLL regenerates clean outputs up to 1.05 GHz for PHY and MAC timing. Jitter attenuation above the loop bandwidth means accumulated system jitter is removed rather than passed through, which is the fundamental difference from a simple zero-delay buffer. The four-input redundancy supports dual-switch-fabric timing sources with automatic failover, improving availability, while the five outputs cover XAUI PHY, management, and fabric-interface clocks from a single IC, reducing BOM count versus discrete PLL-plus-oscillator solutions.
推荐
Fibre Channel SAN Switch Clock Generation
Fibre Channel fabric switches need multiple serializer references (106.25 MHz, 212.5 MHz classes) derived from a single plant-quality source, and the Skyworks datasheet lists Fibre Channel as a primary Si5366 target. The device's 8 kHz to 1050 MHz output range and five differential outputs cover the 1x, 2x, and 4x Fibre Channel rate families from one jitter-cleaned reference. Because fabric ports must meet ANSI T11 jitter budgets end-to-end, cleaning the reference ahead of the serializer PLLs preserves margin that would otherwise be consumed by backplane and distribution-buffer jitter accumulation. Input redundancy lets a SAN director maintain timing through a reference-card swap using automatic failover, and the digitally configured DSPLL bandwidth lets designers trade jitter-transfer bandwidth against jitter cleanup to match the specific switch ASIC's tolerance.
推荐
Central Office BITS/SSU Synchronization Distribution
Carrier central-office equipment must derive all timing from plant BITS/SSU references per GR-1244-class holdover and slip requirements, and the Si5366's four-input architecture with automatic failover is tailored to this role: T1/E1-derived primary, secondary, and GPS references can all terminate on one device, with hitless switching between them. Its 8 kHz low-end input support covers the frame-sync-class references used in plant synchronization, and the DSPLL regenerates timing with jitter well within SONET/SDH mask limits even when the incoming plant reference has degraded after long cable runs. The five outputs distribute cleaned 8 kHz, 19.44 MHz, and derived rates to shelves and line cards. Because the loop filter is integrated, bandwidth and holdover characteristics remain digitally deterministic across temperature and manufacturing variation, simplifying NEBS qualification documentation.
推荐
Optical Transport Network (OTN) Transponder Timing
OTN transponders multiplex client services into OTU2/OTU3 frames, requiring multiple correlated clocks (client, line, and mapping rates) derived from one clean reference. The Si5366 fits this role with four inputs - client recovered clock, line recovered clock, and redundant system references - and five outputs spanning the required rate set within its 8 kHz to 1050 MHz range. The DSPLL's jitter attenuation keeps the line-side serializer reference compliant with OTN timing tolerances even with a noisy client clock as input, and its documented jitter-transfer characteristics simplify ITU-T G.8251 wander/jitter budget calculations. Hitless input switching allows transponder protection schemes to change reference sources without output phase disturbance that would trigger frame loss, which is a hard requirement in carrier protection switching topologies.
推荐
Test and Measurement Instrument Clock Subsystem
Protocol testers, SONET analyzers, and optical test sets need a frequency-agile, jitter-cleaned clock subsystem that can both generate arbitrary test rates and clean recovered clocks from the device under test. The Si5366's any-frequency capability across 8 kHz to 1050 MHz on both inputs and outputs, combined with four selectable inputs, lets one instrument board source many standard and oddball telecom rates without crystal changes, per the Skyworks datasheet frequency range. The DSPLL provides documented, repeatable jitter transfer that testers must characterize and report, and digitally stored configuration allows instant frequency-plan switching under host control - a workflow advantage over analog-PLL designs needing loop-component changes per rate. Five simultaneous outputs serve the DUT reference, analyzer capture clock, and timestamping circuits from one phase-coherent source.
推荐
推荐产品汇总
工程参考数据： Si5366 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | Si5365-C-GQ | Si5367-C-GQ | Si5368-C-GQ | Si5319-C-GM |
|---|---|---|---|---|---|
| Brand | Skyworks Solutions (Silicon Labs timing portfolio) | Skyworks Solutions Inc. | Skyworks Solutions Inc. | Skyworks Solutions Inc. | Skyworks Solutions Inc. |
| PLL Technology | 3rd-generation DSPLL | 3rd-generation DSPLL | 3rd-generation DSPLL | 3rd-generation DSPLL | Earlier DSPLL generation |
| Target Standards | SONET OC-48/OC-192, Ethernet, Fibre Channel | SONET, Ethernet, Fibre Channel | SONET, Ethernet, Fibre Channel | SONET, Ethernet, Fibre Channel | SONET OC-48 class |
关键差异点
- Four inputs with hitless automatic failover （对比 Si5368-C-GQ)
- Up to 1050 MHz output range （对比 Si5367-C-GQ)
- Jitter cleaning (not just synthesis) （对比 Si5368-C-GQ)
- Integrated loop filter vs earlier generation （对比 Si5319-C-GM)
设计说明
Supply noise modulates the DSPLL VCO and appears directly as added jitter. Power the Si5366 core and output supplies from dedicated low-noise LDOs (for example a sub-30 uVrms LDO) rather than shared switcher rails, and decouple each supply pin with 100 nF ceramic capacitors plus a bulk 10 uF per supply domain. Estimated: a 20 mVrms switching ripple on the VCO supply can raise RMS jitter from sub-ps levels into several ps, enough to consume SONET mask margin, so verify with a scope jitter measurement after layout rather than assuming the datasheet floor.
Differential clock inputs and outputs should be routed as 100-ohm coupled pairs with matched lengths and AC-coupled (0.1 uF) where DC levels differ between the Si5366 and the partner ASIC. Avoid routing outputs under the DSPLL supply domain; crosstalk from fast CMOS outputs into the input pair degrades jitter transfer measurements. Terminate differential outputs per the signaling standard used (CML/LVPECL/LVDS) as described in the datasheet output-configuration section, and keep trace stubs under 5 mm at 1 GHz-class output rates.
The Si5366 is register-configured: it will not produce valid outputs until the correct frequency plan is loaded through the serial interface, so a blank-board symptom is usually a configuration issue, not silicon failure. Use Silicon Labs ClockBuilder-style tooling to generate the register map and verify against the Si53xx family reference manual. Also confirm the input frequency lies within 8 kHz to 707 MHz and outputs within 8 kHz to 1050 MHz - requesting an out-of-range plan silently fails. Finally, validate the failover threshold settings so automatic input switching triggers before downstream PLLs unlock.
合规信息
RoHS compliance indicated by distributor listings for the SI5366-C-GQ/GQR SKUs. REACH, halogen-free, and conflict-minerals status not stated in the provided data.