SI5366-B-GQ - Precision Clock Multiplier/Jitter Attenuator | Silicon Labs
料号： SI5366-B-GQ ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
SI5366-B-GQ 概述
A precision clock multiplier/jitter attenuator is a phase-locked-loop (PLL) based timing device that cleans a noisy reference clock and synthesizes a higher-frequency, low-jitter output locked to that reference. In the system hierarchy it sits within the clock generation and distribution layer of the timing chain: oscillator (reference) -> clock multiplier/jitter attenuator -> clock distribution -> SERDES/FPGA/ASIC clocks. Jitter attenuation is essential because the PLL bandpass filters the reference clock, suppressing reference spurs and wander while delivering a stable output at the line rate.
Key features of the SI5366 include four selectable clock inputs spanning 8 kHz to 707 MHz, five frequency-multiplied outputs spanning 8 kHz to 1050 MHz, DSPLL-based jitter cleaning for SONET-grade compliance, and pin-programmable configuration (the B-grade part is set via pin straps rather than in-circuit register programming), simplifying designs that avoid a microcontroller on the timing board. The device operates from a nominal 3.3 V supply per Silicon Labs documentation and is specified for communication-grade temperature ranges.
Technically, the Si5366 uses Silicon Labs' digital DSPLL loop architecture, in which the loop bandwidth is set digitally, providing deterministic jitter transfer and enabling tight reference-to-output frequency mapping suitable for OC-48 (622.08 MHz) and OC-192 (9953.28 MHz SERDES reference) line cards. It replaces discrete VCXO-plus-PLL loops with a single-chip solution and supports hitless reference switching between redundant inputs.
Typical applications include SONET/SDH OTN line cards, 10 GbE and Fibre Channel (1x/2x/4x/10x) transceiver reference clocks, Synchronous Ethernet timing cards, and test equipment clock synthesis. The five outputs allow one device to clock a SERDES, FPGA, PHY, and ASIC simultaneously.
Design consideration: verify the selected loop bandwidth against the applicable jitter transfer mask for your standard, and decouple all supply pins with low-ESR ceramics placed directly at the TQFP power pins.
This page synthesizes distributor availability, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
直接替换替代料： SI5366-B-GQ ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： SI5366-B-GQ （相同外形与封装尺寸） ——差异在于 Input Frequency Range, Output Frequency Range, Package, Maximum Output Frequency, Packaging.
快速对比工具——选择替代料号进行并排对比：
SI5366-A-GQ
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
SI5366-C-GQ
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$28.6 / 个
查看数据手册 →SI5366-B-GQ-SI5
✅ 直接替换📋 参考替代料（不在目录中）
SI5366-B-GQ 规格参数
| Product Type | Precision Clock Multiplier / Jitter Attenuator |
| Number of Clock Inputs | 4 |
| Input Frequency Range | 8 kHz to 707 MHz |
| Number of Clock Outputs | 5 |
| Output Frequency Range | 8 kHz to 1050 MHz |
| Architecture | DSPLL (digital phase-locked loop) |
| Configuration | Pin-programmable (B grade) |
| Target Standards | SONET OC-48/OC-192, Ethernet, Fibre Channel |
| 封装 | 100-TQFP |
| 安装类型 | Surface Mount |
| Packaging | Tray |
SI5366-B-GQ 100-tqfp 引脚配置指南
SI5366-B-GQ（100-tqfp 封装）的引脚配置。 引脚编号、功能和连接图在制造商数据手册中定义。请参阅该手册以了解确切的封装尺寸和焊接指南。
暂无详细引脚数据： SI5366-B-GQ.
请参阅 数据手册 以查看完整引脚配置。
典型应用
SI5366-B-GQ 适用于 6 应用s: SONET OC-48/OC-192 Line Cards, Ethernet Timing Cards, Fibre Channel Systems, Clock Synthesis for Test and Measurement, SONET/SDH Timing Cards and BITS/SSU Equipment, FPGA and ASIC Clocking on Communication Boards.
SONET OC-48/OC-192 Line Cards
The SI5366-B-GQ is explicitly specified in the Si5366 datasheet for SONET OC-48/OC-192 systems, where it multiplies a low-jitter line-card reference (e.g., 19.44 MHz or 155.52 MHz) to the precise line-rate clocks required by OC-48 (622.08 MHz) and OC-192 transceivers. Its DSPLL loop bandpass-filters reference wander and jitter, helping the line card satisfy SONET jitter transfer and generation masks without external analog loop tuning. With four selectable inputs, redundant protection references support hitless reference switching on carrier-grade cards, and the five outputs can simultaneously clock the SERDES, framer, FPGA, and system logic from one reference domain.
推荐
Ethernet Timing Cards
For Synchronous Ethernet and 10GbE equipment, the SI5366-B-GQ generates the low-jitter reference clocks that PHY and SERDES devices require. Its 8 kHz to 707 MHz input range accepts sync-E recovery references or stable 25 MHz/156.25 MHz oscillators, while outputs up to 1050 MHz cover 156.25 MHz, 312.5 MHz, and 625 MHz SERDES reference rates. Per the datasheet, Ethernet is a primary target standard, and the DSPLL jitter attenuation keeps transmitted wander within network limits. The pin-programmable B grade removes the need for in-circuit register configuration, simplifying Ethernet cards that lack a timing-management microcontroller and reducing bring-up effort during production test.
推荐
Fibre Channel Systems
The Si5366 datasheet lists Fibre Channel as a target application, and the SI5366-B-GQ output range of 8 kHz to 1050 MHz supports standard FC reference clock rates for 1x, 2x, and 4x speed grades. In FC storage switches and host bus adapters, the DSPLL attenuates jitter accumulated through backplane clock distribution, protecting transceiver eye margins at multi-gigabit serial rates. Four inputs allow switching between primary and secondary fabric timing sources, and five outputs distribute cleaned clocks to switch ASICs, SERDES, and management PHYs. The 100-TQFP package integrates this capability in a single timing chip, replacing discrete VCXO-plus-PLL loops on the FC line card.
推荐
Clock Synthesis for Test and Measurement
In test and measurement instrumentation, the SI5366-B-GQ provides low-jitter synthesized clocks for ADC/DAC clocking, SerDes stimulus, and timing-reference generation. The 8 kHz to 1050 MHz output span allows one device to derive multiple instrument clock domains from a single stable reference, and the DSPLL architecture delivers deterministic jitter transfer, which matters when instrument phase-noise floors affect measurement uncertainty. Pin-programmable configuration allows fixed-frequency instrument variants to be built without firmware overhead. The four-input architecture also accepts external references (e.g., 10 MHz house standard) for lock to laboratory timing systems.
推荐
SONET/SDH Timing Cards and BITS/SSU Equipment
Central-office timing cards and Building Integrated Timing Supply (BITS) shelves use the SI5366-B-GQ to clean and distribute reference clocks derived from GPS receivers, T1/E1 lines, or OC-3/OC-12 inputs. The 8 kHz lower input limit accommodates low-frequency synchronization references, while DSPLL jitter attenuation ensures the distributed timing meets SDH network limits (e.g., G.813-class masks as applicable to SONET/SDH equipment). Four reference inputs with selection logic enable redundant-reference protection schemes standard in carrier timing. Five outputs fan out to line interfaces and monitoring circuits from one reference domain, reducing component count on high-reliability timing shelves.
推荐
FPGA and ASIC Clocking on Communication Boards
Communication FPGA and ASIC loads frequently need multiple correlated low-jitter clocks, and the SI5366-B-GQ serves this role by deriving up to five outputs from a single reference across 8 kHz to 1050 MHz. Its DSPLL jitter cleaning protects FPGA transceiver reference inputs (e.g., 156.25 MHz or 322.265625 MHz GTH/GTX references) from backplane jitter accumulation, extending serial-link reach and lowering bit-error rates. Pin-programmable configuration means power-rail sequencing and strap settings fully define operation, which simplifies FPGA bring-up on boards without an I2C master during early boot. The 100-TQFP surface-mount package fits standard line-card PCB processes.
推荐
推荐产品汇总
工程参考数据： SI5366-B-GQ ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | SI5366-A-GQ | SI5366-C-GQ | SI5366-B-GQ-SI5 |
|---|---|---|---|---|
| Package | 100-TQFP | 100-TQFP - same | 100-TQFP - same | 100-TQFP - same |
| Brand | Silicon Labs | Silicon Labs | Silicon Labs | Silicon Labs |
| Input Frequency Range | 8 kHz to 707 MHz | 8 kHz to 707 MHz | 8 kHz to 707 MHz | 8 kHz to 707 MHz |
| Output Frequency Range | 8 kHz to 1050 MHz | 8 kHz to 1050 MHz | 8 kHz to 1050 MHz | 8 kHz to 1050 MHz |
| Clock Inputs | 4 | 4 | 4 | 4 |
| Clock Outputs | 5 | 5 | 5 | 5 |
| Jitter Performance Grade | B grade | A grade (different jitter tier) | C grade (different jitter tier) | B grade - same |
| Configuration | Pin-programmable | Pin-programmable | Pin-programmable | Pin-programmable |
| Target Standards | SONET OC-48/OC-192, Ethernet, Fibre Channel | SONET OC-48/OC-192, Ethernet, Fibre Channel | SONET OC-48/OC-192, Ethernet, Fibre Channel | SONET OC-48/OC-192, Ethernet, Fibre Channel |
关键差异点
- Pin-programmable operation without firmware （对比 Si5368)
- Four-input redundant reference architecture （对比 SI5366-A-GQ (same pinout))
- Single-chip SONET-grade jitter attenuation （对比 discrete VCXO + PLL loop)
设计说明
Place low-ESR ceramic decoupling capacitors (100 nF plus bulk 10 uF) directly at each VDD pin of the 100-TQFP, with short, wide traces to solid ground vias. The DSPLL supply rejection is finite, and switching noise on the analog PLL rail appears directly as output jitter on the five clock outputs. Segment the analog PLL supply with a ferrite bead from the digital I/O supply rail, following the reference design guidance in the Si53xx family reference manual from Silicon Labs/Skyworks.
Keep the four reference input traces short, matched in length, and away from the five output traces to prevent crosstalk-induced reference jitter. Outputs up to 1050 MHz should be routed as 50-ohm controlled-impedance lines with series termination close to the driver pin. On multi-layer line cards, provide an unbroken ground reference plane under all clock traces; splitting the plane under a clock line converts it into a common-mode radiator and degrades jitter performance on adjacent receivers.
The B-grade SI5366-B-GQ is pin-programmable, so configuration straps must be stable before and during PLL lock - do not drive straps from a bus that toggles during power-up. Verify that your selected output frequency mapping is supported for your chosen input reference using the configuration tables in the Si5366 datasheet before layout freeze, since not every input/output frequency pair is synthesizable. Also confirm that the chosen DSPLL bandwidth meets the jitter transfer mask of your target standard (SONET OC-48/OC-192, Ethernet, or Fibre Channel).
合规信息
Compliance status not stated in the retrieved web data; verify against the current Silicon Labs (Skyworks) product page and environmental datasheets. Communication timing ICs of this class are typically not AEC-Q100 qualified (commercial/industrial standard grade).