THS1209CDAG4 - 12-Bit 8 MSPS Dual-Channel ADC, 32-TSSOP | TI
料号： THS1209CDAG4 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $9.45 | $9.45 |
| 10 | $8.5 | $85.00 |
| 100 | $7.55 | $755.00 |
| 500 | $6.78 | $3,390.00 |
| 1,000 | $6.05 | $6,050.00 |
THS1209CDAG4 概述
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that samples continuous analog voltages and converts each sample into a discrete digital code. Pipeline and successive-approximation (SAR) ADCs dominate the 8-20 MSPS mid-speed range used in industrial imaging, instrumentation, and DSP front-ends. Within the broader taxonomy, ADCs sit under data converters, which are part of the mixed-signal/interface IC family used in nearly every embedded acquisition system. Pipeline ADCs like the THS1209 favor high sample rates over absolute DC precision; SAR ADCs favor DC accuracy at lower rates. Choosing between them is governed by signal bandwidth, SNR targets, and the latency budget of the downstream DSP.
Key features of the THS1209CDAG4 include 12-bit resolution, 8 MSPS per channel, single 5 V analog supply, low-power CMOS architecture, internal 1.5 V and 3.5 V reference voltages (with optional external reference override), and a hardware-programmable channel autoscan mode. The converter accepts up to two analog inputs simultaneously, so both channels can be captured on the same clock edge without inter-channel skew.
The architecture pairs a high-bandwidth input track-and-hold with a pipelined quantizer, clocked either from an external source or the on-chip oscillator. By integrating reference, track-and-hold, and parallel output logic in one die, the THS1209 eliminates the external sample-and-hold amplifier and reference buffer that older designs required, shrinking the analog front-end footprint considerably. Internal reference voltages of 1.5 V and 3.5 V are provided; an external reference can be selected when tighter DC accuracy or specific temperature drift is required.
Typical applications include ultrasound front-end signal chains, CCD/CIS imaging digitizers, baseband IQ sampling in software-defined radio, motor-control current feedback loops, and multi-channel data-acquisition cards for industrial PCs. The wide input bandwidth and dual-input configuration make it a natural fit for any system that requires synchronized sampling of two analog signals.
When designing with this device, place a 0.1 uF ceramic bypass capacitor directly on each supply pin and a 10 uF bulk capacitor at the analog supply entry; the analog and digital grounds should meet at a single point under the exposed paddle. Verify that the FPGA or DSP driving the parallel interface meets the setup/hold times specified in the datasheet, and route data lines with matched length to avoid capture glitches at 8 MSPS.
This page synthesizes distributor inventory, same-family drop-in alternatives, and practical PCB layout notes drawn from the THS1209 datasheet, providing an engineer-oriented overview not found on any single distributor listing.
直接替换替代料： THS1209CDAG4 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： THS1209CDAG4 （相同外形与封装尺寸） ——差异在于 Architecture, Operating Temperature, Resolution, RoHS Status, Input Configuration.
快速对比工具——选择替代料号进行并排对比：
THS1209CDA
✅ 直接替换📋 参考替代料（不在目录中）
THS1209IDAG4
✅ 直接替换📋 参考替代料（不在目录中）
THS1209IDA
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
THS1209CDAG
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
THS1209CDAG4 最大额定值与电气特性
| 分辨率 | 12 bit |
| 采样率 | 8 MSPS |
| Number of Channels | 2 (single-ended) / 1 (differential) |
| Architecture | Pipelined ADC with simultaneous sampling |
| Input Configuration | 2 single-ended or 1 differential |
| Data Interface | Parallel (DSP/microprocessor-compatible) |
| Channel Autoscan | Yes |
| Analog Supply Voltage | 5 V |
| Digital Supply Voltage | 3.3 V or 5 V |
| Internal Reference Voltages | 1.5 V and 3.5 V |
| External Reference Support | Yes |
| 封装 / 外壳 | 32-TSSOP (DA, 6.10 mm width) |
| 工作温度 | 0C to 70C (commercial grade) |
| Packaging | Tube |
| RoHS 状态 | Compliant |
| 引脚数量 | 32 |
THS1209CDAG4 引脚配置
| 引脚 1 | AVDD — Analog supply voltage (5 V) |
| 引脚 2 | REFLO — Reference low / analog ground |
| 引脚 3 | REFHI — Reference high input (external reference override) |
| 引脚 4 | AINP — Analog input positive (channel 0) |
| 引脚 5 | AINM — Analog input negative / channel 1 |
| 引脚 6 | AGND — Analog ground |
| 引脚 7 | DVDD — Digital supply voltage (3.3 V or 5 V) |
| 引脚 8 | DGND — Digital ground |
| 引脚 9 | CLK — Conversion clock input |
| 引脚 10 | CS — Chip select (active low) |
| 引脚 11 | RD — Read strobe (active low) |
| 引脚 12 | WR — Write strobe for control registers (active low) |
| 引脚 13 | CONVST — Conversion start input |
| 引脚 14 | EOC — End-of-conversion flag (active low) |
| 引脚 15 | D0 — Parallel data output bit 0 (LSB) |
| 引脚 16 | D1 — Parallel data output bit 1 |
| 引脚 17 | D2 — Parallel data output bit 2 |
| 引脚 18 | D3 — Parallel data output bit 3 |
| 引脚 19 | D4 — Parallel data output bit 4 |
| 引脚 20 | D5 — Parallel data output bit 5 |
| 引脚 21 | D6 — Parallel data output bit 6 |
| 引脚 22 | D7 — Parallel data output bit 7 |
| 引脚 23 | D8 — Parallel data output bit 8 |
| 引脚 24 | D9 — Parallel data output bit 9 |
| 引脚 25 | D10 — Parallel data output bit 10 |
| 引脚 26 | D11 — Parallel data output bit 11 (MSB) |
| 引脚 27 | RESET — Hardware reset (active low) |
| 引脚 28 | MODE — Operating mode select (single-ended/differential) |
| 引脚 29 | SCAN — Channel autoscan enable |
| 引脚 30 | NC — Not connected (per datasheet) |
| 引脚 31 | NC — Not connected (per datasheet) |
| 引脚 32 | AVDD — Analog supply voltage (5 V) - second pin |
典型应用
THS1209CDAG4 适用于 6 应用s: Ultrasound Front-End Signal Chain, CCD/CIS Imaging Digitizer, Baseband IQ Sampling in Software-Defined Radio, Motor Control Current Feedback Loop, Multi-Channel Data Acquisition Card, Portable Test & Measurement Instrumentation.
Ultrasound Front-End Signal Chain
The THS1209CDAG4 is well suited to ultrasound receiver front-ends where two channels must be sampled simultaneously. Its 8 MSPS per-channel rate easily captures the 2-5 MHz IF bandwidth typical of diagnostic ultrasound, and the dual simultaneous-sample architecture eliminates inter-channel skew between adjacent transducer elements. Place the part between the LNA/AGC stage and the beamforming FPGA; its 5 V analog supply and on-chip 1.5 V/3.5 V references remove the need for an external reference buffer. Compared with discrete ADC + SHA designs, the integrated track-and-hold reduces analog front-end board area by roughly 30 percent while preserving the 12-bit dynamic range needed for B-mode imaging.
推荐
CCD/CIS Imaging Digitizer
In CCD and CMOS image sensor digitizers the THS1209CDAG4's dual simultaneous sampling inputs correlate two analog channels (such as color-stripe RGB or differential sensor outputs) on the same clock edge, preserving pixel-phase alignment. The parallel 12-bit output feeds directly into an FPGA or DSP color-reconstruction block at rates up to 8 MSPS, supporting line-scan cameras and medical endoscopy heads. Internal references simplify the analog supply tree, while the 32-TSSOP footprint keeps the digitizer compact enough for handheld camera electronics. The trade-off versus higher-resolution ADCs is the 12-bit ceiling; systems needing 14 bits or more should evaluate the THS1408 family instead.
推荐
Baseband IQ Sampling in Software-Defined Radio
For SDR baseband chains, the THS1209CDAG4 captures the I and Q paths from a quadrature demodulator on two simultaneously-clocked inputs at 8 MSPS, producing matched-phase sample pairs for the FFT engine. The 12-bit resolution provides roughly 74 dB of dynamic range, sufficient for many narrowband amateur and industrial monitoring receivers. The parallel interface drops straight into a Spartan-6 or Cyclone IV FPGA without glue logic, and the TSSOP footprint is small enough for a portable handheld radio enclosure. The trade-off is the absence of an on-chip digital decimation filter; that stage must be implemented in the FPGA when channel bandwidths below 1 MHz are required.
推荐
Motor Control Current Feedback Loop
Field-oriented control of three-phase motors demands two simultaneous phase-current samples per PWM cycle, exactly the configuration the THS1209CDAG4 provides through its dual simultaneous inputs. The 8 MSPS rate oversamples the typical 10-20 kHz PWM frequency by a wide margin, leaving headroom for advanced current-ripple compensation algorithms. The 5 V analog supply integrates easily with industrial 24 V bus designs through a small isolated DC-DC converter, and the 32-TSSOP package fits the compact inverter control PCB form factor. Compared with discrete dual-shunt + SAR ADC designs, the THS1209 cuts the analog front-end component count and reduces measurement skew to one clock period.
推荐
Multi-Channel Data Acquisition Card
Industrial PCI/PCIe data-acquisition cards built around the THS1209CDAG4 can digitize up to two channels at 8 MSPS without external sample-and-hold circuitry, dramatically reducing BOM cost. The parallel output bus connects to a host FPGA that packs samples into DMA buffers for the host CPU. Internal 1.5 V and 3.5 V references are adequate for general-purpose 4-20 mA bridge and thermocouple conditioning circuits used in factory automation. The TSSOP-32 footprint allows eight such ADCs to populate a single Eurocard-sized board with channel-to-channel skew controlled by a shared clock distribution tree.
推荐
Portable Test & Measurement Instrumentation
Handheld oscilloscopes, spectrum analyzers, and power-quality meters benefit from the THS1209CDAG4's low power CMOS design and dual-channel sampling at 8 MSPS. Each scope channel pairs naturally with the part's two single-ended inputs, while the differential mode supports floating measurements across isolation barriers. The commercial 0C-70C rating suits laboratory and light-industrial environments; the industrial IDAG4 variant should be selected for outdoor field instruments. The 32-TSSOP package preserves battery life by minimizing quiescent draw and fits inside compact handheld plastic housings alongside an ARM Cortex-M4 display controller.
推荐
推荐产品汇总
工程参考数据： THS1209CDAG4 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | THS1209CDA | THS1209IDAG4 | THS1209IDA | THS1209CDAG |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 32-TSSOP (DA) | 32-TSSOP (DA) - same | 32-TSSOP (DA) - same | 32-TSSOP (DA) - same | 32-TSSOP (DA) - same |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit |
| Sampling Rate | 8 MSPS | 8 MSPS | 8 MSPS | 8 MSPS | 8 MSPS |
| Input Channels | 2 single-ended / 1 differential | 2 single-ended / 1 differential | 2 single-ended / 1 differential | 2 single-ended / 1 differential | 2 single-ended / 1 differential |
| Operating Temperature | 0C to 70C (commercial) | 0C to 70C | -40C to 85C (industrial) | -40C to 85C (industrial) | 0C to 70C |
| Internal Reference | 1.5 V and 3.5 V | 1.5 V and 3.5 V | 1.5 V and 3.5 V | 1.5 V and 3.5 V | 1.5 V and 3.5 V |
| Data Interface | Parallel | Parallel | Parallel | Parallel | Parallel |
| Channel Autoscan | Yes | Yes | Yes | Yes | Yes |
关键差异点
- Industrial temperature variant is a drop-in upgrade （对比 THS1209IDAG4)
- Lead-finish packaging code does not affect performance （对比 THS1209CDA)
- Dual simultaneous sampling eliminates inter-channel skew （对比 Discrete dual-ADC + external SHA design)
设计说明
Place a 0.1 uF ceramic bypass capacitor as close as possible to each AVDD and DVDD pin of the THS1209CDAG4, and add a single 10 uF bulk tantalum or ceramic capacitor at the analog supply entry point. The datasheet recommends tying the analog ground (AGND) and digital ground (DGND) planes together at a single point under the TSSOP body to avoid coupling digital switching noise into the analog front-end. Estimated: at 5 V AVDD and 8 MSPS the supply current approaches the datasheet's worst-case figure, so the bulk capacitor must source this transient demand without the supply drooping below 4.75 V.
Route the parallel D[11:0] data bus with matched trace lengths (within 2 mm) and a 33 ohm series-termination resistor near the THS1209CDAG4 data outputs to damp reflections at 8 MSPS. The CLK, CONVST, and EOC signals should also be length-matched to within 1 cm. Drive CLK from a low-jitter LVCMOS source; jitter greater than 5 ps rms will degrade the ADC SNR noticeably because the input bandwidth exceeds 30 MHz. Keep the analog input traces (AINP/AINM) short and surrounded by a ground guard ring to prevent digital crosstalk.
Power the THS1209CDAG4 from a clean 5 V analog rail - an LDO such as the TPS7A4701RGWR placed upstream of the ADC keeps digital switching noise from upstream converters out of the reference chain. According to the datasheet, the analog supply tolerates 4.75 V to 5.25 V; staying near 5.0 V maximizes the input common-mode range. The DVDD pin can be tied to either 3.3 V or 5 V depending on the FPGA I/O bank voltage, but the input thresholds shift accordingly; verify setup/hold times against the chosen logic level.
Do not leave the MODE and SCAN pins floating - tie them to defined logic levels through 10 kohm resistors to AVDD or DGND. According to the datasheet, floating control inputs can cause unpredictable channel selection or cause the converter to enter a test mode. The RESET pin must be pulsed low at power-up for at least one CLK cycle to initialize internal calibration registers; failure to reset can leave the channel-autoscan state machine in an undefined state and produce non-monotonic data on the first conversions.
Estimated: at maximum 8 MSPS with both channels active and 5 V supplies, the THS1209CDAG4 dissipates roughly 200 mW, producing a junction-temperature rise of about 18C above ambient on a 4-layer JEDEC test PCB (theta_JA approximately 90 C/W for TSSOP-32). At room ambient the junction stays well within the 0C to 70C commercial limit, but designers should derate the analog input range if the enclosure approaches 60C ambient.
合规信息
RoHS and lead-free compliant per TI product page; AEC-Q100 qualification not applicable for the commercial C-grade. For automotive-grade THS1209 variants consult TI's automotive product catalog directly.
