TPS543C20RVFT - 40A Sync Step-Down SWIFT Converter | TI
料号： TPS543C20RVFT ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.2 | $112.00 |
| 100 | $9.85 | $985.00 |
| 500 | $8.4 | $4,200.00 |
| 1,000 | $7.1 | $7,100.00 |
TPS543C20RVFT 概述
A buck (step-down) DC-DC converter is a switching regulator that efficiently converts a higher DC input voltage to a lower DC output voltage by chopping the input with power MOSFETs and smoothing the pulsed waveform through an LC filter. Within the broader power-management hierarchy, buck converters sit between linear regulators (low noise, low efficiency at large VIN-VOUT) and isolated converters; they dominate non-isolated POL applications because switching operation yields 90%+ efficiency even at large step-down ratios.
Key specifications of the TPS543C20RVFT include up to 40 A continuous output current, an internal 4-V to 14-V input range with a 16-V abs-max transient tolerance, sub-1% reference accuracy, and synchronization to an external clock for multi-rail EMI compliance. Differential remote sensing cancels PCB IR drop on the output, preserving load-transient accuracy at the point of load. The package exposes a top-side thermal pad that mates with PCB copper to keep junction temperature within limits at 40 A.
Architecturally, the TPS543C20 uses emulated peak-current-mode control - an internal ramp tracks the inductor current, eliminating the subharmonic instabilities of classic peak-current-mode at high duty cycles. An internal integrator in the control loop further reduces output-ripple sensitivity, so the device needs no external compensation network across the full operating range.
Typical applications include 12-V-input point-of-load regulation for ASICs, FPGAs, and high-current processors; datacom and server POL rails; telecom baseband and memory rails; and any dense board where a stackable second phase can double output current. The wide VIN and high IOUT make it equally suitable for industrial 12-V bus systems.
When designing with the TPS543C20RVFT, follow TI's recommended LC values, place input ceramics as close as possible to the PVIN pins, and use adequate copper area plus thermal vias under the exposed pad. Two TPS543C20 devices can be paralleled for higher IOUT with current sharing.
This page synthesizes distributor pricing, datasheet structure, drop-in alternatives, and PCB layout notes not consolidated on the TI product page.
直接替换替代料： TPS543C20RVFT ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： TPS543C20RVFT （相同外形与封装尺寸） ——差异在于 Clock Synchronization, Control Mode, Input Voltage Range, Output Voltage Range, Package.
快速对比工具——选择替代料号进行并排对比：
TPS543C20RVFR
✅ 直接替换✓ 有现货
$4.38 / 个
查看数据手册 →TPS543C20RVFR
✅ 直接替换✓ 有现货
$4.38 / 个
查看数据手册 →TPS548D21RVFT
✅ 直接替换📋 参考替代料（不在目录中）
TPS546D24A
✅ 直接替换📋 参考替代料（不在目录中）
TPS546E25
✅ 直接替换📋 参考替代料（不在目录中）
TPS543C20RVFT 最大额定值与电气特性
| Product Type | Synchronous Buck (Step-Down) Converter |
| 拓扑 | DC-DC Switching, SWIFT |
| 输入电压范围 | 4 V to 14 V |
| Absolute Max Input Voltage | 16 V |
| 输出电压范围 | 0.6 V to 5.5 V (adjustable) |
| Continuous Output Current | 40 A |
| Output Channels | 1 |
| Control Mode | Internally compensated emulated peak-current-mode |
| Clock Synchronization | Yes (external sync input) |
| Remote Sense | Differential (Kelvin) |
| 软启动 | Programmable / internal |
| 工作温度范围 | -40C to +125C |
| 封装 | 40-pin PowerLFQFN (RVF), exposed thermal pad |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant |
| Feature | Stackable for higher current |
| Telemetry Interface | Optional PMBus / I2C (variant dependent) |
TPS543C20RVFT 引脚配置
| 引脚 1 | PVIN — Power input supply (4 V to 14 V) |
| 引脚 2 | PVIN — Power input supply |
| 引脚 3 | PVIN — Power input supply |
| 引脚 4 | PVIN — Power input supply |
| 引脚 5 | PVIN — Power input supply |
| 引脚 6 | PVIN — Power input supply |
| 引脚 7 | PVIN — Power input supply |
| 引脚 8 | PVIN — Power input supply |
| 引脚 9 | PVIN — Power input supply |
| 引脚 10 | PVIN — Power input supply |
| 引脚 11 | PGND — Power ground return |
| 引脚 12 | PGND — Power ground return |
| 引脚 13 | PGND — Power ground return |
| 引脚 14 | PGND — Power ground return |
| 引脚 15 | PGND — Power ground return |
| 引脚 16 | PGND — Power ground return |
| 引脚 17 | PGND — Power ground return |
| 引脚 18 | PGND — Power ground return |
| 引脚 19 | PGND — Power ground return |
| 引脚 20 | PGND — Power ground return |
| 引脚 21 | VOUT — Regulated output voltage (switch node) |
| 引脚 22 | VOUT — Regulated output voltage |
| 引脚 23 | VOUT — Regulated output voltage |
| 引脚 24 | VOUT — Regulated output voltage |
| 引脚 25 | VOUT — Regulated output voltage |
| 引脚 26 | VOUT — Regulated output voltage |
| 引脚 27 | VOUT — Regulated output voltage |
| 引脚 28 | VOUT — Regulated output voltage |
| 引脚 29 | VOUT — Regulated output voltage |
| 引脚 30 | VOUT — Regulated output voltage |
| 引脚 31 | VSENSE — Differential remote sense (+) input |
| 引脚 32 | VOSNS- — Differential remote sense (-) input |
| 引脚 33 | AGND — Analog ground |
| 引脚 34 | AVIN — Analog input supply (internal LDO) |
| 引脚 35 | EN/UVLO — Enable and undervoltage lockout |
| 引脚 36 | PWRGD — Power-good indicator (open-drain) |
| 引脚 37 | SS/TR — Soft-start / tracking input |
| 引脚 38 | RT/CLK — Frequency setting / external clock sync |
| 引脚 39 | COMP — Compensation node (internal, no external network) |
| 引脚 40 | NC — Not connected (per datasheet) |
典型应用
TPS543C20RVFT 适用于 6 应用s: FPGA/ASIC Point-of-Load Regulation, Datacom and Server Power Rails, Telecom Baseband and Memory Rails, Industrial 12-V Bus POL, AI Accelerator Card POL, Networking Switch ASIC Power.
FPGA/ASIC Point-of-Load Regulation
The TPS543C20RVFT delivers up to 40 A from a 12-V bus to power high-current FPGA core or ASIC rails (typically 0.85 V to 1.2 V) with sub-1% setpoint accuracy. Its emulated peak-current-mode control provides fast transient response to load steps caused by clock-domain transitions in the FPGA. The differential remote sense cancels PCB IR drop so the regulated voltage at the die is exact, critical for timing closure. Stack two devices for 80 A on a single rail.
推荐
Datacom and Server Power Rails
In 12-V distributed-architecture servers, the TPS543C20RVFT converts the bus to 1.0-V/1.8-V/3.3-V intermediate rails for memory, SERDES, and switch ASICs at 40 A per phase. The external clock sync capability phases multiple TPS543C20 devices to eliminate beat-frequency EMI that would otherwise fail CISPR 22 radiated-emissions testing. The 40-pin PowerLFQFN exposed pad handles full-load dissipation with a properly designed 6-layer PCB stackup and thermal vias.
推荐
Telecom Baseband and Memory Rails
The TPS543C20RVFT powers DSP core voltages, DDR memory termination rails, and clock-generator supplies in 4G/5G baseband cards fed from a -48-V to 12-V intermediate bus. Its 4-V to 14-V VIN range tolerates the droop seen on long 12-V backplane traces during transient load events. The internal compensation eliminates the external RC network, freeing board area for additional RF circuitry while keeping the POL BOM to just an inductor, input/output ceramics, and feedback resistors.
推荐
Industrial 12-V Bus POL
Factory automation PLCs and industrial PCs accept 12-V or 24-V backplane power and require isolated, regulated rails for I/O, sensors, and processor cores. The TPS543C20RVFT handles the 12-V bus directly and steps down to 3.3 V or 5 V at 40 A for motor-control DSPs. The -40C to +125C operating junction range and exposed thermal pad suit enclosed industrial cabinets with limited airflow. Two phases can be stacked for higher-power motor drivers.
推荐
AI Accelerator Card POL
Modern AI accelerator cards (training GPUs, inference ASICs) consume hundreds of amps at sub-1-V core voltages. The TPS543C20RVFT stacks four or more devices per rail to deliver 160 A+ while phase-shifting the switching edges to spread EMI across the spectrum. Differential remote sensing ensures regulation at the GPU die despite the IR drop across the high-current bus bars. The exposed thermal pad mates with massive copper pours to dissipate the 100-200 W per converter.
推荐
Networking Switch ASIC Power
Top-of-rack switches and 400G/800G line cards require 40-60 A per ASIC at 0.8 V to 1.0 V, with tight ripple and transient specs for clean SerDes eye diagrams. The TPS543C20RVFT's emulated peak-current-mode control and 1% reference accuracy keep the rail within the ASIC's DC tolerance across load steps. External clock sync aligns all POL converters in the chassis to a single EMI signature, simplifying the radiated-emissions compliance report.
推荐
推荐产品汇总
工程参考数据： TPS543C20RVFT ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | TPS543C20RVFR | TPS548D21RVFT | TPS546D24A | TPS546E25 |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 40-pin PowerLFQFN (RVF) | 40-pin PowerLFQFN (RVF) - same | 40-pin QFN (related family) | 40-pin QFN (related family) | 40-pin QFN (related family) |
| Input Voltage Range | 4 V to 14 V | 4 V to 14 V | 4 V to 16 V (+14% headroom) | 4 V to 16 V | 4.5 V to 18 V |
| Output Current | 40 A | 40 A | 40 A | 40 A | 40 A |
| Output Voltage Range | 0.6 V to 5.5 V | 0.6 V to 5.5 V | 0.6 V to 5.5 V | 0.6 V to 5.5 V | 0.5 V to 5.5 V |
| Automotive Grade | No | No | No | Yes (AEC-Q100) | No |
| Telemetry (PMBus) | Variant dependent | Variant dependent | Yes | Yes | Yes |
| External Clock Sync | Yes | Yes | Yes | Yes | Yes |
| Pin-to-Pin Compatible | (reference) | Yes (same die, reel variant) | No - PCB redesign required | No - PCB redesign required | No - PCB redesign required |
关键差异点
- Internally compensated emulated peak-current-mode control （对比 TPS548D21RVFT)
- Differential remote sensing at the load （对比 TPS546D24A)
- Stackable architecture for 80 A+ outputs （对比 TPS546E25)
- Compact 40-pin PowerLFQFN exposed-pad package （对比 Larger 40-pin QFN variants)
设计说明
At VIN=12 V, VOUT=1.0 V, and 40 A load, the TPS543C20RVFT dissipates approximately 440 mW (P_diss = (VIN - VOUT) x IOUT = (12 - 1) x 40 / efficiency). Although switching losses add another 1-2 W at typical switching frequencies, the total dissipation remains within the 40-pin PowerLFQFN's thermal envelope provided the exposed pad is soldered to a 6-layer PCB with at least 1 sq-in of copper and 9 thermal vias (0.3 mm drill, 1 oz plating). Use TI's EVM thermal layout as a reference for production designs.
Place four 22 uF X7R 25 V ceramic input capacitors as close as possible to the PVIN pins, and connect the PGND returns directly to the top-side ground pour with short, wide traces. Use wide output copper pours (at least 1 oz on outer layers) for VOUT and PGND to handle 40 A continuous. Mount the output inductor and the boot capacitor within 5 mm of the SW node to minimize parasitic inductance that could exceed the IC's absolute-max voltage rating.
Route VSENSE and VOSNS- as a true differential pair directly from the load-side Kelvin connection back to the IC, guarding them with AGND to reject injected noise. Keep the analog ground (AGND) island separate from PGND and tie them together at a single point under the exposed pad. Route the RT/CLK and PWRGD traces away from the SW node to prevent capacitive coupling of switching edges into the analog control loop.
Do not connect VOUT directly to the VSENSE pin at the IC pin - always Kelvin-sense at the load. Do not operate VIN above 16 V, even transiently, or the internal MOSFETs will avalanche and fail. Ensure SS/TR is not left floating - a missing soft-start capacitor causes the converter to start in maximum-duty mode, which can overshoot the output and trigger downstream overvoltage protection.
For multi-phase (stacked) operation, configure the master/slave RT/CLK pins per the datasheet and use matched output inductors (within 10% inductance) to ensure balanced current sharing. Mismatched inductors cause one phase to carry more current than the other, reducing effective SOA and creating thermal hot spots on the PCB. TI's TPS543C20 datasheet application section includes a 2-phase reference schematic.
合规信息
RoHS compliant per TI product page. Commercial/industrial grade - not AEC-Q100 qualified. Choose TPS546D24A for automotive-grade designs.
