TPS546A24 - 10A 18V Stackable PMBus Buck Converter | Texas Instruments
料号： TPS546A24 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $7.5 | $7.50 |
| 10 | $6.78 | $67.80 |
| 100 | $6.05 | $605.00 |
| 500 | $5.45 | $2,725.00 |
| 1,000 | $4.92 | $4,920.00 |
TPS546A24 概述
A buck converter (also known as a step-down switching regulator) is a type of DC-DC converter that efficiently reduces a higher DC input voltage to a lower DC output voltage by rapidly switching an inductor-capacitor filter network. Compared to linear regulators, switching buck converters achieve much higher efficiency (>90%) at high step-down ratios, making them foundational building blocks in modern point-of-load (POL) power management across virtually every electronic system.
Key features include internal 5-V LDO with optional external 5-V overdrive via the VDD5 pin (improves efficiency at high VIN), stackability of up to 4 devices for 40 A on a single output rail, PMBus telemetry for VOUT, IOUT, temperature, and fault monitoring, internal 1.5-V digital regulator (BP1V5), and adaptive dead-time control. The 40-pin RVF QFN package exposes the power pads for thermal dissipation, supporting continuous 10 A output without external heatsinking at moderate VIN/VOUT ratios.
The TPS546A24A uses a peak current-mode control architecture with internal compensation, eliminating the need for external compensation networks and simplifying the external BOM. The device supports pre-biased output startup, frequency synchronization input/output, and 12 pin-strap selectable switching frequencies for multi-rail EMI management. Two-, three-, and four-phase stacking is enabled through dedicated SHARE/SYNC pins, allowing a single TPS546A24A design to scale from 10 A to 40 A simply by adding parallel devices.
Typical applications include data center server POL rails (12 V to 1 V to 3.3 V), telecom and networking equipment, FPGA and ASIC core/IO rails, industrial automation and test equipment, and graphics card memory power. The combination of PMBus monitoring and stackability makes it particularly attractive for advanced telemetry requirements in AI accelerator and high-performance computing designs.
When designing with the TPS546A24A, allocate adequate copper area for the PGND power pads and use the recommended inductor values from the datasheet for stability across the full 225 kHz to 1.5 MHz switching range. The internal compensation is optimized for specific L and C combinations; deviating from these may degrade transient response or load regulation.
This page synthesizes distributor pricing, verified drop-in alternatives (TPS546A24S and TPS546D24A family), and practical design notes not consolidated in the manufacturer datasheet.
直接替换替代料： TPS546A24 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： TPS546A24 （相同外形与封装尺寸） ——差异在于 Continuous Output Current, Control Mode, Digital Interface, Output Voltage Range, Package.
快速对比工具——选择替代料号进行并排对比：
TPS546A24S
✅ 直接替换📋 参考替代料（不在目录中）
TPS546A24AEVM-1PH
✅ 直接替换📋 参考替代料（不在目录中）
TPS546A24ARVFR
✅ 直接替换📋 参考替代料（不在目录中）
TPS546B24ARVFR
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$5.2 / 个
查看数据手册 →TPS546D24ARVFR
✅ 直接替换📋 参考替代料（不在目录中）
TPS546A24 最大额定值与电气特性
| 拓扑 | Synchronous Buck (Step-Down) |
| 输入电压范围 | 2.95 V to 18 V |
| 输出电压范围 | 0.5 V to 5.5 V (adjustable, minimum 0.5 V) |
| Continuous Output Current | 10 A |
| Stackable | Yes, up to 4 phases (40 A total) |
| Switching Frequency Range | 225 kHz to 1.5 MHz |
| Pin-Strap Frequencies | 12 selectable (8 via MSEL pins) |
| Digital Interface | PMBus |
| Internal LDO | 5 V (with optional external overdrive via VDD5) |
| Internal Digital Regulator | 1.5 V (BP1V5) |
| Control Mode | Peak Current-Mode with Internal Compensation |
| 封装 | 40-pin QFN (RVF) PowerLFQFN, 7 mm x 5 mm x 1.5 mm |
| 安装类型 | Surface Mount |
| 工作温度 | -40 C to +125 C junction |
| Pre-Biased Output Support | Yes |
| Frequency Sync | Sync In / Sync Out |
| RoHS 状态 | Compliant |
| MSL 等级 | 2 (per JEDEC J-STD-020) |
TPS546A24 引脚配置
| 引脚 1 | VIN — Input supply voltage |
| 引脚 2 | VIN — Input supply voltage |
| 引脚 3 | VIN — Input supply voltage |
| 引脚 4 | VIN — Input supply voltage |
| 引脚 5 | BP1V5 — Output of 1.5 V internal regulator; bypass with 1 uF X5R 6 V min |
| 引脚 6 | DRTN — Digital bypass return |
| 引脚 7 | AGND — Analog ground |
| 引脚 8 | MSEL1 — Mode select / pin-strap |
| 引脚 9 | MSEL2 — Mode select / pin-strap |
| 引脚 10 | VOUT_SNS — Output voltage sense |
| 引脚 11 | VSEL — Voltage select pin-strap |
| 引脚 12 | FSEL — Frequency select pin-strap |
| 引脚 13 | RT/SS — Resistor timing / soft-start |
| 引脚 14 | COMP — Compensation node |
| 引脚 15 | FB — Feedback (internal) |
| 引脚 16 | PGND — Power ground |
| 引脚 17 | PGND — Power ground |
| 引脚 18 | SW — Switch node |
| 引脚 19 | SW — Switch node |
| 引脚 20 | SW — Switch node |
| 引脚 21 | SW — Switch node |
| 引脚 22 | PGND — Power ground |
| 引脚 23 | PGND — Power ground |
| 引脚 24 | BST — Bootstrap capacitor |
| 引脚 25 | VDD5 — 5 V LDO / external overdrive input |
| 引脚 26 | PGOOD — Power good output |
| 引脚 27 | EN — Enable (active high) |
| 引脚 28 | SHARE — Current share bus |
| 引脚 29 | SYNC — Frequency sync input/output |
| 引脚 30 | SALERT — PMBus alert |
| 引脚 31 | SDA — PMBus data |
| 引脚 32 | SCL — PMBus clock |
| 引脚 33 | ADDR — PMBus address select |
| 引脚 34 | DRTN — Digital bypass return |
| 引脚 35 | NC — Not connected (per datasheet) |
| 引脚 36 | NC — Not connected (per datasheet) |
| 引脚 37 | NC — Not connected (per datasheet) |
| 引脚 38 | NC — Not connected (per datasheet) |
| 引脚 39 | NC — Not connected (per datasheet) |
| 引脚 40 | NC — Not connected (per datasheet) |
典型应用
TPS546A24 适用于 6 应用s: Data Center Server Point-of-Load (POL), FPGA Core and IO Power Rails, Telecom and Networking Equipment, ASIC and Processor Core Power, Industrial Automation and Test Equipment, Graphics Card and GPU Memory Power.
Data Center Server Point-of-Load (POL)
The TPS546A24A's 2.95-V to 18-V input range and 10 A continuous output make it ideal for stepping 12 V bus voltages down to 1 V to 3.3 V POL rails in hyperscale and enterprise servers. With PMBus telemetry for VOUT, IOUT, and junction temperature, system BMC controllers can monitor per-rail health for predictive maintenance. The 4-phase stackability allows 40 A on a single rail for high-current ASIC and AI training workloads.
推荐
FPGA Core and IO Power Rails
The TPS546A24A delivers 0.5 V minimum output voltage with PMBus programmable margining, ideal for Xilinx Versal, Intel Agilex, and Microchip PolarFire FPGA core rails (0.85 V to 1.2 V) and IO rails (1.8 V to 3.3 V). The internal compensation eliminates external component tuning, and the 7x5 mm QFN footprint enables high-density power delivery. Adaptive dead-time control handles fast FPGA load-step transients without external loop tuning.
推荐
Telecom and Networking Equipment
The TPS546A24A's 18-V input tolerance accommodates telecom -48 V systems after an intermediate bus converter (typically 12 V), and its switching frequency range of 225 kHz to 1.5 MHz supports both AM-radio-band avoidance (>1.6 MHz) and high-density designs. Frequency SYNC IN/OUT enables coordinated switching across multiple rails for EMI compliance in carrier-grade routers and switches.
推荐
ASIC and Processor Core Power
The TPS546A24A's PMBus telemetry, adaptive voltage scaling (AVS), and 0.5 V minimum output serve modern ASIC and processor core power requirements where dynamic voltage/frequency scaling (DVFS) is essential for power efficiency. The 12.31 mV/A current sense gain provides accurate load-line regulation across the full 10 A range, while stackability supports multi-core processors requiring 30 A to 40 A sustained current.
推荐
Industrial Automation and Test Equipment
Industrial PLCs, motor controllers, and automated test equipment benefit from the TPS546A24A's -40 C to +125 C junction temperature rating and 18-V tolerance for 24-V industrial bus transients. The PMBus monitoring enables factory-floor diagnostics, and pin-strapping allows zero-firmware configuration for cost-sensitive automation modules. The 4-phase stacking delivers up to 40 A for motor driver and actuator power stages.
推荐
Graphics Card and GPU Memory Power
The TPS546A24A is well-suited for graphics card GDDR6/GDDR7 memory power (1.0 V to 1.35 V) and GPU auxiliary rails where 10 A continuous current and PMBus telemetry are required. The 225 kHz to 1.5 MHz switching range allows small-form-factor inductors and capacitors, enabling compact PCB layouts near the memory devices. Pre-biased output startup prevents reverse-current damage during multi-rail power-up sequencing.
推荐
推荐产品汇总
工程参考数据： TPS546A24 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | TPS546A24S | TPS546A24AEVM-1PH | TPS546A24ARVFR | TPS546D24ARVFR |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | QFN-40 (RVF) 7x5 mm | QFN-40 (RVF) 7x5 mm - same | QFN-40 (RVF) 7x5 mm - same | QFN-40 (RVF) 7x5 mm - same | QFN-40 (RVF) 7x5 mm - same |
| Input Voltage Range | 2.95 V to 18 V | 2.95 V to 18 V | 2.95 V to 18 V | 2.95 V to 18 V | 2.95 V to 16 V |
| Output Current | 10 A | 10 A | 10 A | 10 A | 20 A |
| Current Sense Gain | 12.31 mV/A | 12.31 mV/A | 12.31 mV/A | 12.31 mV/A | 6.155 mV/A |
| PMBus Write Protection | Standard | Extended write protection | Standard | Standard | Standard |
| Switching Frequency | 225 kHz to 1.5 MHz | 225 kHz to 1.5 MHz | 225 kHz to 1.5 MHz | 225 kHz to 1.5 MHz | 225 kHz to 1.5 MHz |
| Drop-In Compatible | Yes (baseline) | Yes (per TI) | Yes (same die) | Yes (same die) | Pin-to-pin, firmware re-tune required |
关键差异点
- Highest input voltage rating (18 V) in 10 A SWIFT™ PMBus family （对比 TPS546D24ARVFR)
- Higher current sense gain for faster transient response （对比 TPS546D24ARVFR)
- Drop-in compatibility with security-enhanced TPS546A24S variant （对比 TPS546A24S)
设计说明
Estimated: at VIN=12 V, VOUT=1 V, and 10 A load, the TPS546A24A dissipates approximately (12-1)*10 = 110 W if linear, but actual switching-mode dissipation is closer to 5 W to 12 W (90%+ efficiency). The 40-pin RVF QFN has a low thermal resistance from the exposed power pads to PCB copper; route at least 4 thermal vias under the central power pad to the opposite copper plane to maintain junction temperature within the -40 C to +125 C rating. Use multiple PCB layers with dedicated PGND planes for optimal heat spreading.
Place input ceramic capacitors (typically 2 x 22 uF X5R 25 V) as close as possible to the VIN pins, and route the SW node traces with minimum loop area to limit EMI. Per the TI datasheet, the BP1V5 pin requires at least 1 uF X5R 6 V minimum bypass directly to DRTN. Avoid routing analog signal traces (FB, COMP) near the SW node to prevent noise injection; shield them with GND traces and via fences.
Do not exceed the 18-V absolute maximum VIN rating, including input transients. The optional external 5-V LDO overdrive via VDD5 must be within the 4.5-V to 5.5-V range; over-voltage on VDD5 can damage internal logic. Per the TI E2E forum, the TPS546A24A and TPS546D24A are pin-to-pin but not firmware-compatible — do not substitute without re-validating compensation and PMBus command tuning. The SHARE pin must be connected for stacked operation and left NC for single-phase use.
The 40-pin RVF QFN requires careful PGND power-pad layout with a via array (typically 4x4 to 5x5 vias at 0.3 mm to 0.5 mm pitch) for thermal dissipation. Per the datasheet, the MSEL and VSEL pin-strap resistors must be placed with short traces to AGND to avoid noise pickup affecting pin-strap decoding. The SYNC pin trace should be routed as a short, isolated signal to prevent coupling with the SW node.
合规信息
RoHS and REACH compliant per TI product page. Halogen-free per TI packaging datasheet. Not AEC-Q100 qualified — not for automotive applications.
