TSA1204IFT - 12-Bit 20MSPS Dual-Channel ADC | STMicroelectronics
料号： TSA1204IFT ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $9.85 | $9.85 |
| 10 | $8.92 | $89.20 |
| 100 | $7.48 | $748.00 |
| 500 | $6.25 | $3,125.00 |
| 1,000 | $5.4 | $5,400.00 |
TSA1204IFT 概述
An Analog-to-Digital Converter (ADC) is a mixed-signal integrated circuit that converts continuous-time analog voltages into discrete digital codes at a specified sampling rate. Dual-channel pipelined ADCs belong to the broader hierarchy of data converter IC -> mixed-signal IC -> semiconductor, and they occupy the performance tier between successive-approximation (SAR) converters (slow, low-power, <5 MSPS) and high-speed flash converters (very fast, very high power). The TSA1204IFT targets moderate-bandwidth multi-channel systems where engineers need two synchronized channels without the cost of two discrete ADCs.
Key features include a 1 GHz analog input bandwidth, an integrated Track-and-Hold amplifier, 11.2-bit effective number of bits (ENOB) at the Nyquist input frequency, and -81.5 dBc spurious-free dynamic range (SFDR) at Nyquist. The 0.25 micrometer CMOS process enables adaptive power consumption scaling from 0.5 MSPS to 20 MSPS, allowing the part to drop to lower power in standby. The CMOS outputs are pin-selectable between 2.5 V and 3.3 V logic levels, simplifying interface to FPGAs, ASICs, or microcontrollers in mixed-voltage systems.
Typical applications include dual-channel digital oscilloscopes, intermediate-frequency (IF) signal processing in communications receivers, ultrasound imaging front-ends, and high-speed industrial data acquisition. The dual channel allows simultaneous sampling of in-phase and quadrature (I/Q) baseband signals, or two channels of a multi-channel instrumentation system.
When designing with the TSA1204IFT, place the analog and digital ground returns on a split ground plane joined under the ADC, use wide PCB traces for the analog supply pins, and decouple each supply pin with 100 nF and 10 uF capacitors placed as close as possible to the device. The exposed pad of the TQFP should be soldered to a ground plane for thermal and electrical performance.
This page synthesizes distributor pricing, drop-in same-family alternatives, and practical design notes not collected in any single manufacturer datasheet revision, giving engineers a one-stop reference for sourcing and second-sourcing the TSA1204IFT.
直接替换替代料： TSA1204IFT ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： TSA1204IFT （相同外形与封装尺寸） ——差异在于 Analog Supply Voltage, Package, Resolution.
快速对比工具——选择替代料号进行并排对比：
TSA1204IPT
✅ 直接替换📋 参考替代料（不在目录中）
TSA1204IPFT
✅ 直接替换📋 参考替代料（不在目录中）
TSA1204IPFTR
✅ 直接替换📋 参考替代料（不在目录中）
TSA1204IFT-E
✅ 直接替换📋 参考替代料（不在目录中）
TSA1204IFT 最大额定值与电气特性
| 分辨率 | 12 bit |
| Number of Channels | 2 (dual) |
| 采样率 | 0.5 MSPS to 20 MSPS |
| Architecture | Pipelined |
| Analog Supply Voltage | 2.5 V (single) |
| Output Logic Supply | 2.5 V / 3.3 V (independent) |
| Power Consumption | 120 mW at 20 MSPS |
| Adaptive Power | 95 mW at 10 MSPS (scales with fs) |
| ENOB at Nyquist | 11.2 bit |
| SFDR at Nyquist | -81.5 dBc |
| Analog Input Bandwidth | 1 GHz |
| Track-and-Hold | Integrated |
| Process Technology | 0.25 um CMOS |
| 封装 | 48-TQFP (7x7 mm) |
| 安装类型 | Surface Mount |
| 工作温度 | -40 C to +85 C (industrial) |
| RoHS 状态 | Compliant |
TSA1204IFT 引脚配置
| 引脚 1 | INA — Analog input channel A |
| 引脚 2 | INTA — Complementary analog input channel A |
| 引脚 3 | VCM — Common-mode voltage reference |
| 引脚 4 | REFB — Bottom reference voltage |
| 引脚 5 | REFT — Top reference voltage |
| 引脚 6 | AGND — Analog ground |
| 引脚 7 | AVDD — Analog supply 2.5 V |
| 引脚 8 | NC — Not connected (per datasheet) |
| 引脚 9 | INB — Analog input channel B |
| 引脚 10 | INTB — Complementary analog input channel B |
| 引脚 11 | CLK — Clock input |
| 引脚 12 | CLKT — Complementary clock input |
| 引脚 13 | DGND — Digital ground |
| 引脚 14 | OVDD — Output supply 2.5/3.3 V |
| 引脚 15 | D0A — Data output A bit 0 (LSB) |
| 引脚 16 | D1A — Data output A bit 1 |
| 引脚 17 | D2A — Data output A bit 2 |
| 引脚 18 | D3A — Data output A bit 3 |
| 引脚 19 | D4A — Data output A bit 4 |
| 引脚 20 | D5A — Data output A bit 5 |
| 引脚 21 | D6A — Data output A bit 6 |
| 引脚 22 | D7A — Data output A bit 7 |
| 引脚 23 | D8A — Data output A bit 8 |
| 引脚 24 | D9A — Data output A bit 9 |
| 引脚 25 | D10A — Data output A bit 10 |
| 引脚 26 | D11A — Data output A bit 11 (MSB) |
| 引脚 27 | DGND — Digital ground |
| 引脚 28 | OVDD — Output supply 2.5/3.3 V |
| 引脚 29 | D0B — Data output B bit 0 (LSB) |
| 引脚 30 | D1B — Data output B bit 1 |
| 引脚 31 | D2B — Data output B bit 2 |
| 引脚 32 | D3B — Data output B bit 3 |
| 引脚 33 | D4B — Data output B bit 4 |
| 引脚 34 | D5B — Data output B bit 5 |
| 引脚 35 | D6B — Data output B bit 6 |
| 引脚 36 | D7B — Data output B bit 7 |
| 引脚 37 | D8B — Data output B bit 8 |
| 引脚 38 | D9B — Data output B bit 9 |
| 引脚 39 | D10B — Data output B bit 10 |
| 引脚 40 | D11B — Data output B bit 11 (MSB) |
| 引脚 41 | OEA — Output enable channel A |
| 引脚 42 | OEB — Output enable channel B |
| 引脚 43 | NC — Not connected (per datasheet) |
| 引脚 44 | DGND — Digital ground |
| 引脚 45 | AVDD — Analog supply 2.5 V |
| 引脚 46 | AGND — Analog ground |
| 引脚 47 | REFT — Top reference voltage (second pin) |
| 引脚 48 | REFB — Bottom reference voltage (second pin) |
典型应用
TSA1204IFT 适用于 7 应用s: Dual-Channel Digital Oscilloscope, Communications IF Sampling, Ultrasound Imaging Front-End, Industrial Data Acquisition Systems, Radar and Lidar Signal Processing, Video and Imaging Digitization, Test and Measurement Instrumentation.
Dual-Channel Digital Oscilloscope
The TSA1204IFT suits dual-channel digital oscilloscope front-ends where two synchronized 12-bit samples per conversion cycle are needed. With 20 MSPS per channel, 1 GHz analog input bandwidth, and 11.2-bit ENOB at Nyquist, the part captures repetitive and single-shot waveforms across the oscilloscope's vertical bandwidth without aliasing. The independent 2.5 V/3.3 V CMOS output supply lets the ADC drive an FPGA capture buffer directly, eliminating level-shift translators and saving PCB area. Adaptive power scaling at lower time-base settings reduces dissipation during long-acquisition runs.
推荐
Communications IF Sampling
The TSA1204IFT is well-matched to intermediate-frequency (IF) sampling in software-defined radio and digital receivers. The dual channels allow simultaneous I/Q baseband capture or two diversity branches, while the 1 GHz analog input bandwidth comfortably covers IF stages up to several hundred MHz. ENOB of 11.2 bits at Nyquist preserves modulation fidelity for QAM and OFDM demodulation, and the 0.25 um CMOS pipeline architecture delivers low latency suitable for real-time signal processing. The 2.5 V analog supply keeps power dissipation in densely populated receiver boards manageable.
推荐
Ultrasound Imaging Front-End
Medical ultrasound beamformers need many synchronized analog channels digitized at moderate rates - a use case that fits the TSA1204IFT's dual-channel 20 MSPS architecture. The 12-bit resolution and -81.5 dBc SFDR preserve the dynamic range required for low-contrast tissue imaging, while the 1 GHz analog input bandwidth handles the broadband piezoelectric transducer signals. Adaptive power scaling at lower frame rates cuts system heat in portable cart-based systems. Two channels per package lower BOM cost compared with discrete single-channel ADCs.
推荐
Industrial Data Acquisition Systems
Multi-channel industrial data acquisition modules use the TSA1204IFT to digitize sensor arrays at 20 MSPS aggregate. The dual-channel pipelined design lets one IC service two sensor channels - vibration and temperature-conditioned transducers, for example - while preserving channel-to-channel synchronization critical for phase analysis. The integrated Track-and-Hold eliminates external sample-and-hold circuits, and the 2.5 V analog supply interfaces directly to industrial 3.3 V sensor front-ends. Extended industrial temperature grade supports factory-floor deployment.
推荐
Radar and Lidar Signal Processing
Automotive and industrial radar/lidar front-ends demand dual-channel moderate-speed ADCs to capture return signals from two antenna or photodiode channels simultaneously. The TSA1204IFT's 20 MSPS rate and 1 GHz input bandwidth suit short-range FMCW radar and pulsed lidar receivers where signal bandwidth rarely exceeds a few hundred MHz. The 11.2-bit ENOB provides sufficient amplitude resolution for target classification, and the 48-TQFP package exposes the thermal pad to ground copper for stable performance in enclosed sensor housings.
推荐
Video and Imaging Digitization
Broadcast and pro-video digitizing equipment benefits from the TSA1204IFT's dual-channel 20 MSPS rate when capturing component video or two synchronized SDI streams at lower resolutions. The 12-bit resolution captures professional-grade color depth, and the -81.5 dBc SFDR prevents visible artifacts from spurious tones in chroma channels. Independent 2.5 V/3.3 V CMOS output levels interface directly to FPGA fabric used for scaling and color-space conversion. Adaptive power scaling helps when the equipment idles between active captures.
推荐
Test and Measurement Instrumentation
Bench instruments such as spectrum analyzers, arbitrary waveform generators with feedback paths, and modular data acquisition cards use the TSA1204IFT for its dual-channel synchronization. The 1 GHz analog bandwidth preserves fast edges in measurement feedback loops, while the 11.2-bit ENOB at Nyquist supports accurate amplitude measurements across the instrument's frequency span. The 48-TQFP package with exposed pad provides reliable thermal performance in densely populated instrument mainboards, where many ADCs sit near heat-generating analog front-ends.
推荐
推荐产品汇总
工程参考数据： TSA1204IFT ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | TSA1204IPT | TSA1204IPFT | TSA1204IPFTR | TSA1204IFT-E |
|---|---|---|---|---|---|
| Package | 48-TQFP (7x7 mm) | 48-TQFP (7x7 mm) - same | 48-TQFP (7x7 mm) - same | 48-TQFP (7x7 mm) - same | 48-TQFP (7x7 mm) - same |
| Brand | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit |
| Sampling Rate | 20 MSPS | 20 MSPS | 20 MSPS | 20 MSPS | 20 MSPS |
| Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) |
| ENOB at Nyquist | 11.2 bit | 11.2 bit | 11.2 bit | 11.2 bit | 11.2 bit |
| SFDR at Nyquist | -81.5 dBc | -81.5 dBc | -81.5 dBc | -81.5 dBc | -81.5 dBc |
| Analog Supply | 2.5 V | 2.5 V | 2.5 V | 2.5 V | 2.5 V |
| Output Logic | 2.5 V / 3.3 V CMOS | 2.5 V / 3.3 V CMOS | 2.5 V / 3.3 V CMOS | 2.5 V / 3.3 V CMOS | 2.5 V / 3.3 V CMOS |
关键差异点
- True 20 MSPS dual-channel simultaneous sampling in 48-TQFP （对比 MAX1306ECM+T (12-channel) and TLV2545IDGKR (slow 12-bit SAR))
- 1 GHz analog input bandwidth for IF undersampling （对比 TLV2545IDGKR (1.5 MHz input bandwidth))
- Pin-selectable 2.5 V / 3.3 V CMOS output supply （对比 MAX197BEWI (5 V analog / parallel))
- Adaptive power scaling from 0.5 MSPS to 20 MSPS （对比 THS1040CPWRG4 (fixed-power 40 MSPS))
设计说明
Use a four-layer PCB with split analog and digital ground planes joined only under the TSA1204IFT exposed pad. Route analog input traces as 50 ohm differential pairs (INA/INTA and INB/INTB) and keep digital output buses (D0A-D11A, D0B-D11B) routed on the opposite side to avoid coupling noise into the analog front-end. Place 100 nF X7R ceramic bypass capacitors within 2 mm of every AVDD and OVDD pin, with a single 10 uF tantalum or ceramic bulk capacitor at the supply entry point.
Drive AVDD with a low-noise LDO such as the TPS7A4701 from a clean 5 V rail, since the 1 GHz analog input bandwidth makes the part sensitive to supply noise that couples into the input stage. The independent OVDD can be driven from a separate 3.3 V rail if interfacing to a 3.3 V FPGA. Add a small ferrite bead between AVDD and OVDD pins to suppress digital switching noise from coupling into the analog supply. Total power dissipation is 120 mW at 20 MSPS - no heatsink required.
The TSA1204IFT output bus switches 24 CMOS lines on every clock edge at 20 MSPS, creating fast edge rates that radiate. Source-terminate each output with a 33 ohm series resistor close to the ADC pin to damp reflections on the transmission-line path to the FPGA. Match CLK/CLKT trace lengths within 1 mm to preserve duty cycle at the ADC clock input. Place a clock buffer near the ADC if the FPGA clock output drives more than two ADC clock pins to avoid excessive loading.
Do not leave REFT and REFB floating - they must be decoupled with 100 nF capacitors to AGND to stabilize the internal reference ladder. Avoid driving the analog inputs beyond the absolute maximum rating of AVDD + 0.3 V; AC-couple or clamp the inputs if the upstream signal exceeds this range. The exposed thermal pad must be soldered to the ground plane for both thermal dissipation and electrical reference - skipping this pad connection degrades linearity.
合规信息
RoHS and lead-free status confirmed from ST product family information; AEC-Q100 not applicable for this commercial/industrial-grade part.
