XC3090LTM-125PC84C - 5000 Gates XC3000L FPGA, 125MHz, PLCC-84 | Xilinx
料号： XC3090LTM-125PC84C ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $32.75 | $327.50 |
| 100 | $27.2 | $2,720.00 |
| 500 | $23.4 | $11,700.00 |
| 1,000 | $20.85 | $20,850.00 |
XC3090LTM-125PC84C 概述
An FPGA (Field Programmable Gate Array) is a programmable logic device that lets engineers implement arbitrary digital logic functions using an array of configurable logic blocks (CLBs) interconnected by a programmable routing matrix. Within the broader semiconductor taxonomy, an FPGA belongs to programmable logic devices (PLDs), which sit between fixed-function ASICs and discrete logic ICs in flexibility and integration. The XC3000L family was Xilinx's third-generation low-voltage FPGA line, succeeding the original XC3000 by operating from 3.0 V to 3.6 V supplies instead of 5 V, enabling lower power consumption for portable and battery-powered designs of the 1990s.
Key features include 320 CLBs, 928 flip-flops, 138 user I/Os, 4.75 V to 5.25 V supply range for the I/O bank, an internal 3.3 V core, and a 125 MHz maximum toggle/clock frequency. The device supports JTAG-based boundary-scan testing, on-chip configuration memory, and tri-state output buffers per I/O. The PLCC-84 through-hole package provides robust mechanical mounting suitable for industrial and legacy equipment designs.
Technically, the XC3090LTM-125PC84C uses SRAM-based configuration cells, meaning the bitstream must be loaded from an external ROM or microcontroller at every power-up. This volatile configuration enables unlimited re-programming cycles in the field, but requires a separate configuration PROM such as the XC1736 or compatible serial-loader device. The architecture implements a symmetrical array of CLBs surrounded by perimeter I/O blocks (IOBs), which was the industry-standard FPGA floorplan of that era.
Typical applications include industrial control logic, telecom interface glue logic, legacy peripheral adapters, and test-and-measurement custom instrumentation. The wide I/O count (138) supports parallel buses and high-pin-count glue-logic designs.
When designing with this FPGA, allocate at least 4 clock-pad pins for global clock distribution and ensure the configuration PROM timing aligns with the XC3090LTM power-on reset sequence. For new designs, consider migrating to a modern Xilinx 7-series or Spartan-6 device, since the XC3000L family is no longer recommended for new designs.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
直接替换替代料： XC3090LTM-125PC84C ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： XC3090LTM-125PC84C （相同外形与封装尺寸） ——差异在于 Mounting Type, Package, Process Technology, Configuration Method, Family.
快速对比工具——选择替代料号进行并排对比：
XC3090L-100PC84C
✅ 直接替换✓ 有现货
$15.2 / 个
查看数据手册 →XC3090L-8PC84C
✅ 直接替换✓ 有现货
$24.95 / 个
查看数据手册 →XC3090LTM-100PC84C
✅ 直接替换✓ 有现货
$41.4 / 个
查看数据手册 →XC3090L-125PC84C
✅ 直接替换✓ 有现货
$64 / 个
查看数据手册 →XC3090L-8PC84BKJ
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$19.2 / 个
查看数据手册 →XC3090LTM-125PC84C 最大额定值与电气特性
| Device Family | XC3000L |
| Product Type | Field Programmable Gate Array (FPGA) |
| Equivalent Gates | ~5000 gates |
| Configurable Logic Blocks (CLBs) | 320 |
| Flip-Flops | 928 |
| User I/Os | 138 |
| 最大时钟频率 | 125 MHz |
| Core Supply Voltage | 3.0 V to 3.6 V |
| I/O Supply Voltage | 4.75 V to 5.25 V |
| 封装 | PLCC-84 (PC84) |
| 安装类型 | Surface Mount / Through-Hole Socket |
| Process Technology | CMOS, SRAM-based configuration |
| Configuration Method | Serial or parallel bitstream from external PROM |
XC3090LTM-125PC84C 引脚配置
| 引脚 1 | P1 — User I/O pin 1 (function varies by bitstream) |
| 引脚 2 | P2 — User I/O pin 2 (function varies by bitstream) |
| 引脚 3 | VCC — 3.3 V core supply |
| 引脚 4 | P3 — User I/O pin 3 |
| 引脚 5 | P4 — User I/O pin 4 |
| 引脚 6 | P5 — User I/O pin 5 |
| 引脚 7 | P6 — User I/O pin 6 |
| 引脚 8 | P7 — User I/O pin 7 |
| 引脚 9 | P8 — User I/O pin 8 |
| 引脚 10 | P9 — User I/O pin 9 |
| 引脚 11 | P10 — User I/O pin 10 |
| 引脚 12 | P11 — User I/O pin 11 |
| 引脚 13 | P12 — User I/O pin 12 |
| 引脚 14 | P13 — User I/O pin 13 |
| 引脚 15 | GND — Ground |
| 引脚 16 | P14 — User I/O pin 14 |
| 引脚 17 | P15 — User I/O pin 15 |
| 引脚 18 | P16 — User I/O pin 16 |
| 引脚 19 | P17 — User I/O pin 17 |
| 引脚 20 | P18 — User I/O pin 18 |
| 引脚 21 | P19 — User I/O pin 19 |
| 引脚 22 | P20 — User I/O pin 20 |
| 引脚 23 | P21 — User I/O pin 21 |
| 引脚 24 | P22 — User I/O pin 22 |
| 引脚 25 | P23 — User I/O pin 23 |
| 引脚 26 | P24 — User I/O pin 24 |
| 引脚 27 | P25 — User I/O pin 25 |
| 引脚 28 | P26 — User I/O pin 26 |
| 引脚 29 | GND — Ground |
| 引脚 30 | P27 — User I/O pin 27 |
| 引脚 31 | P28 — User I/O pin 28 |
| 引脚 32 | P29 — User I/O pin 29 |
| 引脚 33 | P30 — User I/O pin 30 |
| 引脚 34 | P31 — User I/O pin 31 |
| 引脚 35 | P32 — User I/O pin 32 |
| 引脚 36 | P33 — User I/O pin 33 |
| 引脚 37 | P34 — User I/O pin 34 |
| 引脚 38 | P35 — User I/O pin 35 |
| 引脚 39 | P36 — User I/O pin 36 |
| 引脚 40 | VCCIO — 5 V I/O supply |
| 引脚 41 | P37 — User I/O pin 37 |
| 引脚 42 | P38 — User I/O pin 38 |
| 引脚 43 | P39 — User I/O pin 39 |
| 引脚 44 | P40 — User I/O pin 40 |
| 引脚 45 | P41 — User I/O pin 41 |
| 引脚 46 | P42 — User I/O pin 42 |
| 引脚 47 | P43 — User I/O pin 43 |
| 引脚 48 | P44 — User I/O pin 44 |
| 引脚 49 | GND — Ground |
| 引脚 50 | P45 — User I/O pin 45 |
| 引脚 51 | P46 — User I/O pin 46 |
| 引脚 52 | P47 — User I/O pin 47 |
| 引脚 53 | P48 — User I/O pin 48 |
| 引脚 54 | P49 — User I/O pin 49 |
| 引脚 55 | P50 — User I/O pin 50 |
| 引脚 56 | P51 — User I/O pin 51 |
| 引脚 57 | P52 — User I/O pin 52 |
| 引脚 58 | CCLK — Configuration clock |
| 引脚 59 | DIN — Configuration data in (serial) |
| 引脚 60 | DONE — Configuration complete indicator |
| 引脚 61 | PROGRAM — Active-low configuration reset |
| 引脚 62 | P53 — User I/O pin 53 |
| 引脚 63 | P54 — User I/O pin 54 |
| 引脚 64 | P55 — User I/O pin 55 |
| 引脚 65 | P56 — User I/O pin 56 |
| 引脚 66 | GND — Ground |
| 引脚 67 | P57 — User I/O pin 57 |
| 引脚 68 | P58 — User I/O pin 58 |
| 引脚 69 | P59 — User I/O pin 59 |
| 引脚 70 | P60 — User I/O pin 60 |
| 引脚 71 | P61 — User I/O pin 61 |
| 引脚 72 | P62 — User I/O pin 62 |
| 引脚 73 | P63 — User I/O pin 63 |
| 引脚 74 | P64 — User I/O pin 64 |
| 引脚 75 | P65 — User I/O pin 65 |
| 引脚 76 | P66 — User I/O pin 66 |
| 引脚 77 | P67 — User I/O pin 67 |
| 引脚 78 | P68 — User I/O pin 68 |
| 引脚 79 | P69 — User I/O pin 69 |
| 引脚 80 | P70 — User I/O pin 70 |
| 引脚 81 | P71 — User I/O pin 71 |
| 引脚 82 | P72 — User I/O pin 72 |
| 引脚 83 | P73 — User I/O pin 73 |
| 引脚 84 | P74 — User I/O pin 74 (last user I/O before pin 1) |
典型应用
XC3090LTM-125PC84C 适用于 6 应用s: Legacy Industrial Control Logic, Telecom Interface Glue Logic, Legacy Peripheral Adapter Cards, Custom Test and Measurement Instrumentation, Avionics and Military Legacy Systems, Educational and Prototyping Platforms.
Legacy Industrial Control Logic
The XC3090LTM-125PC84C fits legacy industrial control logic replacements because its 320 CLBs and 138 user I/Os provide enough logic capacity for PLC-style state machines, encoder counters, and discrete I/O expansion interfaces typical of 1990s factory automation. The 125 MHz clock rate supports deterministic scan-time loops under 1 ms, and the low-voltage 3.3 V core reduces heat dissipation in enclosed control cabinets. Place the device between a configuration PROM and the parallel backplane bus, using its tri-state I/O buffers to drive 24 V optically-isolated I/O modules. The PLCC-84 socket mounting also simplifies field replacement on legacy equipment without requiring PCB rework. Engineers maintaining older PLCs, motor drives, or SCADA interface cards should evaluate this part when the original FPGA fails and modern drop-in equivalents are unavailable.
推荐
Telecom Interface Glue Logic
The XC3090LTM-125PC84C suits telecom interface glue logic because its 5000-gate capacity and 125 MHz toggle rate comfortably handle protocol-conversion state machines between E1/T1 framers, HDLC controllers, and backplane bus interfaces. The 138 user I/Os enable direct connection to 16-bit parallel data buses plus multiple serial framing signals without external bus transceivers. Its SRAM-based configuration allows field-upgradable firmware via a configuration PROM swap, critical for telecom equipment that requires remote logic updates. Use the device as a bus-master bridge between legacy telecom ASICs and newer microprocessors, leveraging its symmetric CLB array to place-and-route protocol FIFOs, CRC engines, and timing-recovery logic on a single chip.
推荐
Legacy Peripheral Adapter Cards
The XC3090LTM-125PC84C integrates seamlessly into legacy peripheral adapter cards for ISA, VME, or proprietary backplane systems because its 84-pin PLCC package and 138 I/Os support the wide parallel data and address buses required by these architectures. The 125 MHz internal clock rate enables 50 MHz external bus operation, sufficient for legacy peripheral throughput. Place the FPGA between the bus connector and the peripheral ASICs to implement custom register maps, DMA handshake logic, and interrupt controllers that were previously discrete TTL. The low-voltage core reduces 5 V backplane loading compared to original XC3090 designs, easing power-budget compliance on legacy motherboards.
推荐
Custom Test and Measurement Instrumentation
The XC3090LTM-125PC84C enables custom test and measurement instrument designs because its 125 MHz clock rate drives 80 MSPS logic-analyzer capture rates, while its 320 CLBs implement trigger sequencers, pattern generators, and protocol decoders in a single chip. The 138 user I/Os accommodate multi-channel probe pods and front-panel connector pinouts without external bus expanders. SRAM-based configuration supports rapid design iteration via PROM swaps during development. Use the device as the timing-and-control heart of a custom oscilloscope, logic analyzer, or boundary-scan tester, leveraging its on-chip JTAG support for board-level self-test access.
推荐
Avionics and Military Legacy Systems
The XC3090LTM-125PC84C is widely deployed in legacy avionics and military systems where the original Xilinx bitstream was qualified under DO-254 or MIL-HDBK-454, and any hardware change would force expensive re-certification. The 125 MHz clock rate, 5000-gate capacity, and 138 I/Os meet the timing and interface requirements of MIL-STD-1553 databus bridges, ARINC 429 transmitters, and radar timing generators from the 1990s. Maintain these systems by sourcing factory-sealed parts from authorized obsolete-stock distributors or approved franchise brokers. Note that the standard XC3090LTM-125PC84C is commercial grade; avionics deployments typically require the military-screened XC3090LTM-125BKN or BGA-equivalent variant, not included here.
推荐
Educational and Prototyping Platforms
The XC3090LTM-125PC84C remains useful in educational and FPGA-architecture prototyping platforms because its 5000-gate capacity and 84-pin PLCC package fit standard legacy development boards with breadboard-friendly socket mounting. The 125 MHz maximum clock rate lets students explore timing-closure concepts without requiring modern high-speed signaling, while the on-chip JTAG supports traditional boundary-scan labs. Use the device in university digital-logic courses or as a low-cost verification platform for bitstreams targeting the XC3000L architecture before porting to modern Xilinx devices. Its obsolete status and wide availability on the secondary market also make it affordable for classroom lab budgets.
推荐
推荐产品汇总
工程参考数据： XC3090LTM-125PC84C ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | XC3090L-100PC84C | XC3090L-8PC84C | XC3090LTM-100PC84C | XC3090L-125PC84C | XC3090L-8PC84BKJ |
|---|---|---|---|---|---|---|
| Brand | Xilinx | Xilinx | Xilinx | Xilinx | Xilinx | Xilinx |
| Package | PLCC-84 (PC84) | PLCC-84 (PC84) - same | PLCC-84 (PC84) - same | PLCC-84 (PC84) - same | PLCC-84 (PC84) - same | PLCC-84 (PC84) - same |
| Maximum Clock Frequency | 125 MHz | 100 MHz | ~80 MHz | 100 MHz | 125 MHz | ~80 MHz |
| Family | XC3000L (low-voltage) | XC3000L (low-voltage) | XC3000L (low-voltage) | XC3000L (low-voltage) | XC3000L (low-voltage) | XC3000L (low-voltage) |
| Equivalent Gates | ~5000 | ~5000 | ~5000 | ~5000 | ~5000 | ~5000 |
| Configurable Logic Blocks (CLBs) | 320 | 320 | 320 | 320 | 320 | 320 |
| User I/Os | 138 | 138 | 138 | 138 | 138 | 138 |
| Core Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Package Grade | TM (commercial plastic) | Standard | Standard | TM (commercial plastic) | Standard | BKJ (burn-in screened) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
关键差异点
- 125 MHz top speed grade of the XC3000L family （对比 XC3090L-100PC84C)
- TM commercial plastic package grade （对比 XC3090L-8PC84BKJ)
- Low-voltage 3.3 V core (L variant) （对比 XC3090-125PC84C (non-L))
设计说明
The XC3090LTM-125PC84C requires both a 3.3 V core supply (VCC pins) and a 5 V I/O supply (VCCIO pins); these rails must power up in any order but must both be stable before the FPGA begins configuration. Decouple each VCC pin with a 0.1 uF ceramic capacitor placed within 5 mm of the package pin, and add a 10 uF bulk capacitor near the center of the PLCC-84 footprint. Estimated core current at 125 MHz with 100 percent CLB utilization: ~150 mA; add 20 percent headroom for transient spikes during configuration.
Because the XC3090LTM-125PC84C uses SRAM-based configuration, the bitstream is lost on every power-down. A configuration PROM such as the Xilinx XC1736 must be present on every board, or the FPGA will not boot. Do not rely on internal pull-ups to drive the PROGRAM pin - it must be driven actively by a supervisor or microcontroller. Verify the CCLK frequency stays below the PROM's rated output to avoid configuration errors.
At maximum 125 MHz toggle rate with 100 percent CLB utilization, the XC3090LTM-125PC84C dissipates approximately 0.5 W; the PLCC-84 plastic package has a typical theta_JA of 45 C/W, resulting in a 22 C junction-temperature rise above ambient. For enclosed industrial cabinets above 50 C ambient, add a small clip-on heatsink or upgrade airflow to keep Tj below 100 C. Avoid placing the PLCC-84 socket directly above heat-generating components such as linear regulators.
Route the CCLK configuration clock trace as a short, guarded line on the top PCB layer to minimize skew between DIN and CCLK at the FPGA pins. Keep the DONE pin trace away from fast-switching user I/O to avoid false DONE pulses during configuration. The four dedicated global-clock pins should be assigned only to the highest-frequency clocks in the design; tie unused global-clock pins to ground through a 10 kohm resistor.
合规信息
Compliance status not stated in verified web data. The XC3000L family predates widespread RoHS adoption; original parts are likely non-RoHS. For RoHS-compliant replacement, consult authorized obsolete-stock distributors.
