XC3090L-8PC84C - 320-Cell XC3000 FPGA | AMD Xilinx | 84-PLCC
MPN: XC3090L-8PC84C β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $42.5 | $42.50 |
| 10 | $36.8 | $368.00 |
| 100 | $31.25 | $3,125.00 |
| 500 | $27.4 | $13,700.00 |
| 1,000 | $24.95 | $24,950.00 |
Drop-in alternatives for XC3090L-8PC84C β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
XC3190A-4PC84C
β Drop-Inπ Reference alternative (not in catalog)
XC3064A-7PC84C
β Drop-Inπ Reference alternative (not in catalog)
XC3042A-7PC84C
β Drop-Inπ Reference alternative (not in catalog)
XC3090L-7PC84C
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
XC3090-100PC84C
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
XC3090L-8PC84C Maximum Ratings & Electrical Characteristics
| Product Type | Field Programmable Gate Array (FPGA) |
| Series | XC3000A/L |
| Gates (Usable) | 6,000 |
| Logic Cells (CLBs) | 320 |
| Configuration Memory | 64,160 bits |
| User I/O Pins | 70 |
| Maximum Toggle Frequency | 80 MHz |
| Supply Voltage | 3.3 V (L variant) |
| Speed Grade | -8 |
| Operating Temperature Grade | Commercial (C) |
| Package Type | 84-pin PLCC (J-lead) |
| Mounting Type | Surface Mount / Socket |
| Boundary Scan | JTAG IEEE 1149.1 |
| Configuration Mode | Serial / Parallel / Boundary-Scan |
XC3090L-8PC84C Pin Configuration
| Pin 1 | I/O β User I/O pin (refer to datasheet for specific bank assignment) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | I/O β User I/O pin |
| Pin 6 | I/O β User I/O pin |
| Pin 7 | I/O β User I/O pin |
| Pin 8 | I/O β User I/O pin |
| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | I/O β User I/O pin |
| Pin 12 | GND β Ground |
| Pin 13 | I/O β User I/O pin |
| Pin 14 | I/O β User I/O pin |
| Pin 15 | I/O β User I/O pin |
| Pin 16 | I/O β User I/O pin |
| Pin 17 | I/O β User I/O pin |
| Pin 18 | I/O β User I/O pin |
| Pin 19 | I/O β User I/O pin |
| Pin 20 | I/O β User I/O pin |
| Pin 21 | I/O β User I/O pin |
| Pin 22 | I/O β User I/O pin |
| Pin 23 | M0 β Configuration mode select 0 |
| Pin 24 | M1 β Configuration mode select 1 |
| Pin 25 | M2 β Configuration mode select 2 |
| Pin 26 | VCC β +3.3 V supply (L variant) |
| Pin 27 | I/O β User I/O pin |
| Pin 28 | I/O β User I/O pin |
| Pin 29 | I/O β User I/O pin |
| Pin 30 | I/O β User I/O pin |
| Pin 31 | I/O β User I/O pin |
| Pin 32 | I/O β User I/O pin |
| Pin 33 | I/O β User I/O pin |
| Pin 34 | I/O β User I/O pin |
| Pin 35 | I/O β User I/O pin |
| Pin 36 | I/O β User I/O pin |
| Pin 37 | I/O β User I/O pin |
| Pin 38 | GND β Ground |
| Pin 39 | I/O β User I/O pin |
| Pin 40 | I/O β User I/O pin |
| Pin 41 | I/O β User I/O pin |
| Pin 42 | I/O β User I/O pin |
| Pin 43 | I/O β User I/O pin |
| Pin 44 | I/O β User I/O pin |
| Pin 45 | I/O β User I/O pin |
| Pin 46 | I/O β User I/O pin |
| Pin 47 | I/O β User I/O pin |
| Pin 48 | I/O β User I/O pin |
| Pin 49 | I/O β User I/O pin |
| Pin 50 | VCC β +3.3 V supply |
| Pin 51 | I/O β User I/O pin |
| Pin 52 | I/O β User I/O pin |
| Pin 53 | I/O β User I/O pin |
| Pin 54 | I/O β User I/O pin |
| Pin 55 | I/O β User I/O pin |
| Pin 56 | I/O β User I/O pin |
| Pin 57 | I/O β User I/O pin |
| Pin 58 | I/O β User I/O pin |
| Pin 59 | I/O β User I/O pin |
| Pin 60 | I/O β User I/O pin |
| Pin 61 | I/O β User I/O pin |
| Pin 62 | I/O β User I/O pin |
| Pin 63 | GND β Ground |
| Pin 64 | CCLK β Configuration clock |
| Pin 65 | DONE β Configuration complete indicator |
| Pin 66 | INIT β Configuration initialization |
| Pin 67 | I/O β User I/O pin |
| Pin 68 | I/O β User I/O pin |
| Pin 69 | I/O β User I/O pin |
| Pin 70 | I/O β User I/O pin |
| Pin 71 | I/O β User I/O pin |
| Pin 72 | I/O β User I/O pin |
| Pin 73 | I/O β User I/O pin |
| Pin 74 | I/O β User I/O pin |
| Pin 75 | I/O β User I/O pin |
| Pin 76 | I/O β User I/O pin |
| Pin 77 | I/O β User I/O pin |
| Pin 78 | I/O β User I/O pin |
| Pin 79 | I/O β User I/O pin |
| Pin 80 | VCC β +3.3 V supply |
| Pin 81 | TDI β JTAG Test Data In (IEEE 1149.1) |
| Pin 82 | TMS β JTAG Test Mode Select |
| Pin 83 | TCK β JTAG Test Clock |
| Pin 84 | TDO β JTAG Test Data Out |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
XC3090L-8PC84C is suitable for 6 applications: Legacy Industrial Control Systems, Telecom Line-Card Glue Logic, ASIC Prototyping and Emulation, Educational FPGA Laboratory Platforms, Retrocomputing and Test Equipment Repair, Aerospace and Defense Obsolescence Management.
Legacy Industrial Control Systems
The XC3090L-8PC84C was widely deployed in 1990s-era industrial control and SCADA interface boards where its 320 CLBs and 70 user I/O provided enough logic density for glue functions, motor control sequencers, and parallel I/O expansion. The 84-pin PLCC package allowed socketed field replacement, an important feature for downtime-critical factory lines. Modern retrofits should match the original pinout, retain the JTAG boundary-scan for production test access, and validate that 3.3 V supply rails remain within the L-variant spec.
Recommended
Telecom Line-Card Glue Logic
In legacy T1/E1 line cards and DSLAM backplanes, the XC3090L-8PC84C served as a flexible glue-logic device bridging framers, LIUs, and network processors. Its 80 MHz toggle rate comfortably handled DS1/E1 bit timing, while the 70 user I/O supported multiple parallel control buses. The 3.3 V L variant simplified power tree design in mixed 3.3 V/5 V systems. Service technicians maintaining these cards today can use modern JTAG programmers to verify configuration without removing the chip from the socket.
Recommended
ASIC Prototyping and Emulation
Before the era of multi-million-gate FPGAs, the XC3090L-8PC84C was used to prototype ASICs in the 5,000-8,000 gate range, particularly in industrial, automotive, and consumer silicon designs. Engineers mapped RTL to the XC3000 LUT structure and validated timing using the XACTstep M1 timing analyzer. The PLCC package enabled rapid board spins during design iterations. While modern ASIC prototyping uses large FPGAs, the XC3090L remains valuable for emulating and validating legacy ASICs in long-life aerospace and defense systems.
Recommended
Educational FPGA Laboratory Platforms
Universities adopted the XC3090L-8PC84C in undergraduate and graduate digital-design labs because its 320 CLBs and PLCC socket were ideal for teaching Verilog/VHDL synthesis, place-and-route fundamentals, and JTAG configuration flow. The 84-pin PLCC accepts zero-insertion-force sockets, allowing students to swap parts during lab sessions without soldering. The XC3000 architecture remains pedagogically valuable for understanding five-input LUTs and distributed configuration memory before transitioning to modern FPGA curricula.
Recommended
Retrocomputing and Test Equipment Repair
The XC3090L-8PC84C powers vintage test instruments, data acquisition boards, and retrocomputing peripherals originally sold in the late 1990s. Restorers of gear like logic analyzers, custom GPIB interfaces, and early video processing boards rely on the XC3090L for socketed replacement. Sourcing authentic parts requires contacting authorized surplus distributors such as Lisleapex or Xecor; no modern Xilinx FPGA replicates the exact 84-pin PLCC footprint, so the original part remains essential for faithful restoration.
Recommended
Aerospace and Defense Obsolescence Management
Aerospace and defense programs with 20-30 year field-life requirements must manage the XC3090L-8PC84C through its obsolete lifecycle. Programs stock lifetime-buy quantities, qualify trusted third-party distributors, and design adapter boards that allow modern replacements such as the XC3190A-4PC84C or XC2S50 to be tested in place. The JTAG boundary-scan per IEEE 1149.1 remains essential for in-system verification during the part's long service life.
Recommended
Recommended Products Summary
Engineering reference data for XC3090L-8PC84C β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | XC3190A-4PC84C | XC3064A-7PC84C | XC3042A-7PC84C | XC3090L-7PC84C | XC3090-100PC84C |
|---|---|---|---|---|---|---|
| Package | 84-pin PLCC (J-lead) | 84-pin PLCC (J-lead) - same | 84-pin PLCC (J-lead) - same | 84-pin PLCC (J-lead) - same | 84-pin PLCC (J-lead) - same | 84-pin PLCC (J-lead) - same |
| Brand | Xilinx (AMD) | Xilinx (AMD) | Xilinx (AMD) | Xilinx (AMD) | Xilinx (AMD) | Xilinx (AMD) |
| Logic Cells (CLBs) | 320 | Higher density (XC3100A family) | 224 (-30%) | 144 (-55%) | 320 (same) | 320 (same) |
| Supply Voltage | 3.3 V (L variant) | 5 V | 5 V or 3.3 V variant | 5 V or 3.3 V variant | 3.3 V | 5 V |
| User I/O | 70 | 70 | 70 | 70 | 70 | 70 |
| Speed Grade | -8 (slowest) | -4 | -7 | -7 | -7 (faster) | -100 |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| JTAG Boundary Scan | Yes (IEEE 1149.1) | Yes | Yes | Yes | Yes | Yes |
Key Differentiators
- Low-voltage 3.3 V supply variant of the XC3090 family (vs XC3090-100PC84C)
- Pin-compatible with the broader XC3000A/L PLCC-84 family (vs XC3190A-4PC84C)
- Established JTAG boundary-scan for production test (vs XC3042A-7PC84C)
Design Notes
Place 0.1 uF decoupling capacitors as close as possible to every VCC pin (pins 26, 50, 80) and the GND pins (12, 38, 63). For an 84-pin PLCC with three VCC and three GND pins, use six 0.1 uF ceramics distributed around the package perimeter. Add a single 10 uF tantalum or ceramic bulk capacitor near the FPGA's VCC entry point. The XC3000 family is sensitive to power-supply noise during configuration; insufficient decoupling causes CRC errors and configuration failure.
Configuration mode pins M0, M1, M2 (pins 23, 24, 25) must be held stable throughout the configuration process. Floating mode pins cause the FPGA to enter an undefined state. Tie them to defined logic levels via 4.7 kohm resistors to VCC or GND. The DONE pin (65) is open-drain and requires a 4.7 kohm pull-up to VCC; omitting this pull-up prevents the downstream system from recognizing successful configuration completion.
Estimated: At 80 MHz toggle rates, the XC3090L-8PC84C generates edge rates near 1-2 ns. Trace lengths on CCLK (pin 64) and global clock nets should be kept under 50 mm with series damping of 33 ohm near the driver. Use a ground reference plane under all clock and high-speed I/O traces to control impedance near 50 ohm. For multi-card systems, add 22 ohm series resistors at clock driver outputs to dampen reflections.
Compliance Information
RoHS status for the legacy XC3090L-8PC84C PLCC package is not documented in the retrieved 2026-09-13 data; this part predates the RoHS transition and may require exemption analysis for new designs. AEC-Q100 is not applicable for FPGAs of this vintage.
