EPM5064JC-2 vs EPM5064JC مقارنة
مقارنة تفصيلية جنبًا إلى جنب لـ EPM5064JC-2 بواسطة Altera و EPM5064JC بواسطة Altera. قارن المواصفات الرئيسية والمعلمات الكهربائية والتغليف وحالة دورة الحياة والأسعار والتوافر لتحديد أفضل مكوّن لمتطلبات تصميمك.
مقارنة المواصفات
| المعامل | EPM5064JC-2 | EPM5064JC |
|---|---|---|
| العلامة التجارية | Altera | Altera |
| الفئة | FPGA & CPLD | FPGA & CPLD |
| حالة دورة الحياة | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | — |
| Propagation Delay (tPD) | 45 ns | — |
| Maximum Clock Frequency (fMAX) | 50 MHz | — |
| Usable Gates | 1250 | 1,250 (approx.) |
| Dedicated Inputs | 7 | — |
| I/O Pins | 28 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V (typical, 4.75 V - 5.25 V range) |
| Programming Method | UV-erase + EPROM programmer (not ISP) | — |
| العلبة | 28-pin CLCC (J-lead, ceramic, windowed) | 68-pin PLCC (JEDEC) |
| درجة حرارة التشغيل | [DATA_NEEDED: commercial or industrial grade] | [DATA_NEEDED: operating temperature grade] |
| Compliance | RoHS status unknown (ceramic/J-lead windowed part, legacy product) | — |
| Device Type | — | EPLD (Erasable PLD) |
| Logic Array Inputs | — | 36 |
| Logic Array Outputs | — | 64 |
| نوع التركيب | — | Surface Mount (socketed) |
| I/O Logic Level | — | TTL / CMOS compatible |
| Configuration Memory | — | EPROM (UV-erasable window or OTP) |
| Pin-to-Pin Delay (tPD) | — | [DATA_NEEDED: specific tPD grade value] |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fCNT grade value] |
| حالة RoHS | — | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| مستوى MSL | — | [DATA_NEEDED: MSL rating] |
| Programming Tool | — | Altera MAX+PLUS II / Quartus II (legacy device support) |