EPM5064JC-2 vs EPM5064JC Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5064JC-2 sa pamamagitan ng Altera at EPM5064JC sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5064JC-2 EPM5064JC
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 MAX 5000
Macrocells 64 64
Logic Array Blocks (LABs) 4 —
Propagation Delay (tPD) 45 ns —
Maximum Clock Frequency (fMAX) 50 MHz —
Usable Gates 1250 1,250 (approx.)
Dedicated Inputs 7 —
I/O Pins 28 —
Interconnect Programmable Interconnect Array (PIA) —
Technology CMOS, UV-erasable EPROM —
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) 5 V (typical, 4.75 V - 5.25 V range)
Programming Method UV-erase + EPROM programmer (not ISP) —
Packhaging 28-pin CLCC (J-lead, ceramic, windowed) 68-pin PLCC (JEDEC)
Temperature na Operasyon [DATA_NEEDED: commercial or industrial grade] [DATA_NEEDED: operating temperature grade]
Compliance RoHS status unknown (ceramic/J-lead windowed part, legacy product) —
Device Type — EPLD (Erasable PLD)
Logic Array Inputs — 36
Logic Array Outputs — 64
Uri ng Pagpapasok — Surface Mount (socketed)
I/O Logic Level — TTL / CMOS compatible
Configuration Memory — EPROM (UV-erasable window or OTP)
Pin-to-Pin Delay (tPD) — [DATA_NEEDED: specific tPD grade value]
Maximum Frequency (fMAX) — [DATA_NEEDED: fCNT grade value]
Tindminan RoHS — [DATA_NEEDED: RoHS compliance]
Lead-Free — [DATA_NEEDED: lead-free status]
Level ng MSL — [DATA_NEEDED: MSL rating]
Programming Tool — Altera MAX+PLUS II / Quartus II (legacy device support)

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