Clock & Timing
Products (160)
SI5335C-B-GM - 4-Output Any-Freq Clock Generator (<350 MHz) | Skyworks
The Skyworks Solutions (formerly Silicon Labs) SI5335C-B-GM is a web-customizable, any-frequency, any-output quad clock generator housed in a 24-pin QFN package. The base part number SI5335C-B-GM identifies the unprogrammed factory default configuration; the full ordering code is completed with a customer-specific 5-digit frequency code at the -B suffix. The device synthesizes four non-integer-related output frequencies between 1 MHz and 350 MHz and supports any mix of differential (LVPECL, LVDS, HCSL) or single-ended (LVCMOS, SSTL) output formats from a single device. A clock generator (also called a frequency synthesizer or clock generator IC) is a timing IC that produces one or more reference-grade output clocks from a single input reference, replacing multiple crystal oscillators and reducing BOM cost in systems that previously required separate XOs for each frequency. Modern quad clock generators with MultiSynth fractional dividers extend this concept by allowing all four outputs to run on independent, non-integer-related frequencies, eliminating frequency-planning restrictions at the architecture stage. Key features of the Si5335C family include a frequency range of 1 MHz to 350 MHz per output, sub-200 fs RMS phase jitter (12 kHz to 20 MHz), four independent MultiSynth fractional divider blocks, and five user-defined pins (3, 5, 6, 12, 19) selectable via the ClockBuilder utility. The 24-pin QFN package has a small 4x4 mm footprint and supports storage temperatures from -65 °C to +150 °C. Internally the Si5335C uses a PLL locked to a 2.5–50 MHz external reference, followed by Skyworks' patented MultiSynth fractional-N divider architecture that provides 0 ppm frequency synthesis error on every output independently. Per-bank supply pins (3.3 V, 2.5 V, 1.8 V, 1.5 V) mean each output bank can drive a different logic level without level translators, simplifying multi-format designs. Typical applications include telecom and networking line cards, multi-rate Ethernet PHYs, FPGA and processor reference clocks, PCIe Gen 2/3 reference generation, and broadcast video equipment where multiple unrelated frequencies must coexist. Per the manufacturer, the part is supplied in an industrial temperature grade. When designing in the Si5335C, drive the device with a clean external crystal or CMOS reference and use Skyworks' ClockBuilder desktop utility to generate the per-order factory-programmed NVM image before submitting your unique B-suffix code. Per the datasheet, output format, output enable polarity, and I²C address are configured via the B-code, not by external strapping. This page synthesizes distributor pricing, drop-in B-code ordering variants, and practical ClockBuilder workflow notes that supplement the manufacturer datasheet.
SI5335C-B02329-GMR - Quad Clock Generator <350MHz, 24-QFN | Skyworks
The Skyworks Solutions (formerly Silicon Labs) SI5335C-B02329-GMR is a web-customizable, any-frequency, any-output quad clock generator housed in a 24-pin QFN (4x4 mm) exposed-pad package. It synthesizes four completely non-integer-related frequencies up to 350 MHz with 0 ppm frequency synthesis accuracy using Skyworks' patented MultiSynth fractional divider technology. A clock generator is a semiconductor device that produces one or more periodic reference signals used to synchronize digital logic, data converters, communications PHYs, and microcontrollers. Clock generators sit within the broader clock and timing hierarchy: clock generator -> timing IC -> clock & timing -> integrated circuit. They typically replace multiple crystal oscillators (XOs) and provide frequency flexibility through I2C/SPI configuration, with sub-ps jitter performance when designed correctly. Key features of the SI5335C-B02329-GMR include four output banks supporting one differential pair or two single-ended outputs each (eight single-ended outputs maximum), a wide 0.16 to 350 MHz output frequency range per bank, configurable input reference (crystal, CMOS, differential), and per-output enable and frequency programming via the Skyworks ClockBuilder Pro software. The 24-QFN exposed-pad package provides low thermal resistance (theta-JA approximately 38 C/W) and a small PCB footprint suitable for space-constrained designs. At the architectural level, the device combines a low-noise integer PLL front end with four independent MultiSynth fractional output dividers. The PLL multiplies the reference frequency to an internal VCO rate, and each MultiSynth block further divides and fractionalizes this to produce arbitrary output frequencies without requiring external VCXO tuning. Internal regulators supply clean core power, and the I2C interface supports in-system configuration without hardware strapping. Typical applications include FPGA clock trees (Xilinx 7-series, Intel Cyclone), communications line-card timing, multi-rate ADC/DAC sampling clocks, server/storage backplane reference generation, broadcast video reference timing, and industrial control backplanes. The ability to derive four independent outputs from a single reference reduces BOM cost and PCB area versus discrete XO solutions. When designing with the SI5335C, place the input reference and load capacitors close to the XIN/XOUT pins, route each output to its load with controlled impedance and short traces, and connect the exposed pad to a solid ground pour for thermal dissipation. Decouple each VDD pin with 0.1 uF plus 1 uF ceramic capacitors placed as close as physically possible to the IC. This page synthesizes real distributor pricing, true drop-in pin-compatible Si5335 family variants, and practical PCB layout guidance not consolidated in the manufacturer datasheet alone.
SI5335C-B07520-GM - 4-Output Clock Generator, 350 MHz, QFN-24 | Skyworks
The Skyworks (formerly Silicon Labs) SI5335C-B07520-GM is a web-customizable, any-frequency, any-output quad clock generator housed in a 24-pin QFN (4x4 mm) exposed-pad package. The device synthesizes four completely non-integer-related output clocks up to 350 MHz from a single reference input, with each of four output banks supporting either one differential pair or two single-ended CMOS outputs. Per the Skyworks Si5335 datasheet, frequency plans are factory-customized via the ClockBuilder Pro utility, and the on-chip MultiSynth fractional dividers eliminate the need for external VCXOs or crystal oscillators for most frequency plans. A clock generator IC (also called a frequency synthesizer or clock multiplier) is a timing device that derives one or more precise output frequencies from a single low-frequency reference source such as a crystal or oscillator. Within the broader IC taxonomy it sits under Clock & Timing ICs -> Clock Generator -> Timing IC -> Power Management and Signal Chain IC. Modern clock generators like the Si5335 family integrate PLLs with fractional-N dividers (MultiSynth) to produce arbitrary non-integer-related frequencies without the spurs typical of integer-N synthesizers, replacing legacy solutions built from discrete PLL + VCXO + divider chains. Key differentiating specifications include four independently-programmable output banks, output frequency range of 1 MHz to 350 MHz, low typical RMS phase jitter of sub-ps on select frequencies, integrated 2.5 V or 3.3 V LDO regulators permitting single 1.8 V / 2.5 V / 3.3 V supply operation, and five user-defined pins (pins 3, 5, 6, 12, 19) that the ClockBuilder Pro utility can customize for functions such as OE, FS, SS, PD, or frequency select. The exposed thermal pad of the QFN-24 package provides a low theta_JA thermal path for reliable operation across -40C to +85C ambient. The IC also features configurable spread-spectrum capability for EMI mitigation in consumer and industrial designs. The Si5335C architecture pairs a high-frequency integer PLL with four independent MultiSynth fractional output dividers, allowing each output to have a unique frequency unrelated to the others by any integer ratio. This is critical for systems that require CPU clock, DDR memory clock, PCIe reference clock, and an audio or video clock from a single device. The internal LDOs isolate the analog PLL supply from the noisy digital output supply, contributing to the part's strong jitter performance. Typical applications include networking switches and routers, FPGA-based designs (Xilinx 7-series, Intel Cyclone, Lattice ECP5), telecom base-station timing, multi-rate audio/video broadcast equipment, server and storage controller boards, and test-and-measurement instrumentation. When laying out the Si5335C, place the reference input crystal or LVCMOS source within 5 mm of the REF input pin, route each differential output pair with matched 100 ohm differential microstrip or stripline, and stitch the exposed pad with at least 9 thermal vias for low ground impedance. The datasheet recommends 0.1 uF decoupling close to each VDD pin and a 1 uF bulk capacitor near the exposed pad. This page consolidates distributor pricing, drop-in alternatives, and PCB design notes not found in a single point in the manufacturer datasheet.
SI5338A-B-GM - 710MHz Any-Frequency Clock Generator, 24-QFN | Skyworks
The Skyworks SI5338A-B-GM is a high-performance, low-jitter I2C-programmable any-frequency clock generator capable of synthesizing independent frequencies on each of four output drivers up to 710 MHz, packaged in a 24-pin 4x4 mm QFN with exposed pad. It accepts an input reference from 5 MHz to 710 MHz and generates four independently programmable outputs with 0 ppm synthesis precision using Skyworks' patented MultiSynth technology, replacing up to four discrete crystal oscillators on a single 24-QFN footprint. A clock generator is a timing integrated circuit that produces one or more precise reference frequencies from a single input reference, eliminating the need for multiple crystal oscillators. Clock generators sit hierarchically under timing ICs, which in turn belong to the broader category of power management and clock tree devices. Modern any-frequency clock generators use fractional-N or digital PLL architectures to synthesize non-integer output frequencies without needing custom quartz crystals, dramatically simplifying BOM and sourcing for multi-protocol designs. Key features of the SI5338A-B-GM include an input reference range of 5 MHz to 710 MHz, four independently configurable outputs from 0.16 MHz to 710 MHz, typical RMS jitter below 0.7 ps (12 kHz to 20 MHz), an I2C control interface with on-chip non-volatile EEPROM for stand-alone configuration, and selectable output formats including LVDS, LVPECL, HCSL, CMOS, and SSTL. Supply voltage is 2.97 V to 3.63 V for the core, with separate output driver supplies at 1.71 V to 1.98 V or 2.25 V to 2.75 V. The device uses a digital PLL architecture with MultiSynth fractional dividers, allowing truly arbitrary frequency synthesis without the classic fractional-N spurs. Internal loop bandwidth and jitter attenuation are user-tunable via I2C registers, enabling optimization for both OCXO-referenced telecom systems and crystal-referenced Ethernet or PCIe applications. The 24-QFN exposed pad provides a thermal resistance of approximately 38 C/W, supporting industrial-grade operation from -40C to +85C. Typical applications include Ethernet switch and PHY clocking, Fibre Channel and PCIe reference clocks, telecom timing cards with SONET/SDH or SyncE hierarchies, and multi-protocol FPGA or processor clock trees. Industrial test equipment and broadcast video systems also benefit from the four independent outputs on a single footprint. When designing with this device, place the input reference crystal or oscillator within 5 mm of the REF pin and route the REF clock trace over a continuous ground plane to minimize jitter. The exposed pad must be soldered to a continuous ground plane with at least 16 thermal vias for proper heat dissipation and electrical performance. This page synthesizes distributor pricing from DigiKey and Mouser, drop-in alternatives in the same 24-QFN package, and practical design notes not found in the manufacturer datasheet. Engineers searching for SI5338A-B-GM datasheets, pinouts, pricing, and cross-references will find consolidated technical information optimized for component selection.
SI5338C-A-GM - I2C Clock Generator, 200MHz, 4-Output | Skyworks
The Skyworks (formerly Silicon Labs) SI5338C-A-GM is an I2C-programmable, any-frequency, any-output quad clock generator IC delivering up to 200 MHz on four differential outputs from a single 24-pin QFN (4x4 mm) package. It uses proprietary MultiSynth fractional-N divider technology to synthesize four independently programmable output frequencies, replacing multiple crystal oscillators and complex discrete PLLs. The device operates from a 2.5 V / 3.3 V core supply plus an independent output supply rail. A clock generator (or frequency synthesizer) is a timing IC that produces one or more precise reference frequencies derived from a single input reference, typically a low-cost crystal or crystal oscillator. It belongs to the broader category of clock and timing ICs, which also includes buffers, multiplexers, jitter cleaners, and phase-locked loops (PLLs). In modern digital systems, clock generators sit at the top of the timing tree and feed downstream PHYs, SoCs, FPGAs, and memory controllers, so their jitter and frequency accuracy directly bound the performance of the entire board. Key features include any-frequency synthesis from 0.16 MHz to 200 MHz on each output, sub-200 fs RMS typical phase jitter (12 kHz to 20 MHz), four differential output drivers that can also be configured as eight single-ended CMOS clocks, I2C control interface for in-circuit reconfiguration, and a field-programmable variant via the Si5338/56-PROG-EVB. Independent output voltage rails (1.8 V, 2.5 V, or 3.3 V) eliminate level shifters when driving mixed-voltage logic. Architecturally, the Si5338C-A-GM integrates a low-noise integer-N PLL plus four independent MultiSynth fractional-N divider blocks, each with its own output driver. This dual-stage design achieves the wide frequency range of fractional synthesis while keeping the jitter contribution of the dividers low. The I2C interface exposes a 364-byte configuration RAM that the host can rewrite at any time, allowing in-system frequency changes for FPGA bitstream reconfiguration or link-rate switching. Typical applications include Ethernet switch PHY clocking (10/100/1G/10G), PCI Express Gen 1/2/3 reference clocks, Fibre Channel port timing, telecom line cards, FPGA fabric and transceiver reference clocks, and any system that needs multiple independent frequencies from one crystal reference. The 24-QFN (4x4) footprint is friendly to compact router and switch designs. When designing with this part, place the input reference crystal within 5 mm of the XIN/XOUT pins and route the output traces with controlled 50 ohm impedance. Verify the in-circuit I2C configuration script against your board's frequency plan before bringing up the system, since a wrong MultiSynth setting will appear as an output stuck at the wrong rate. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the standalone Si5338 datasheet.
SI5338K-B-GM - 4-Output I2C Clock Generator 0.16-710 MHz | Skyworks
The Skyworks Solutions SI5338K-B-GM is an I2C-programmable any-frequency, any-output quad clock generator housed in a 24-pin QFN (4x4 mm) package, capable of synthesizing four completely non-integer-related frequencies between 0.16 MHz and 710 MHz. The device targets Ethernet, Fibre Channel, PCI Express (PCIe), and Telecom reference-clock applications where multiple unrelated output frequencies must be generated from a single low-cost reference. A clock generator IC is a timing device that synthesizes one or more output reference clocks from a single input reference or crystal, multiplying, dividing, or translating the input frequency into the user-required outputs. Clock generators belong to the broader category of clock and timing ICs, which also includes clock buffers, PLL clock drivers, and jitter cleaners; they are the foundational timing building blocks of nearly every digital system that requires synchronous logic. Key features of the Si5338K include four output banks (each bank supporting one differential pair or two single-ended outputs), per-bank output enable control, I2C control of frequency and format, integrated MultiSynth fractional dividers, low RMS phase jitter, and a single OEB pin that can disable all outputs simultaneously. The Skyworks datasheet confirms operation from a 2.5 V / 3.3 V core supply and supports LVCMOS, LVDS, HCSL, and CML output formats from independently configured banks. Architecturally the Si5338K uses a wide-range MultiSynth fractional divider stage per output, allowing the four outputs to be completely independent and non-integer-related without requiring multiple external oscillators. This single-chip architecture replaces up to four discrete XOs or VCXOs, reducing BOM cost and PCB area on Ethernet switches, PCIe add-in cards, and storage controllers. Typical applications include Ethernet switch/router reference clocks, Fibre Channel SAN HBAs, PCI Express Gen 2/3 endpoint and root-complex reference clocks, telecom line cards, FPGA and ASIC reference-clock trees, and industrial test equipment. The device is also used as a low-jitter replacement for multiple crystal oscillators on dense motherboards. When designing with the Si5338K-B-GM, ensure that the input reference (crystal or LVCMOS) meets the datasheet frequency and stability requirements, and that the I2C pull-ups are sized for the bus capacitance. Decouple VDD pins with 0.1 uF and 10 uF capacitors placed as close as possible to the package, and respect the exposed-pad soldering guidelines for the 24-QFN thermal pad. This page synthesizes distributor pricing from DigiKey, Mouser, Arrow, and Octopart, drop-in Skyworks same-family alternatives already in production, and practical PCB-level design notes that go beyond the manufacturer datasheet.
SI5340A-B05364-GM - 4-Output Ultra-Low Jitter Clock Generator | Skyworks
The Skyworks Solutions SI5340A-B05364-GM is an ultra-low jitter, 4-output, any-frequency, any-output clock generator housed in a 44-pin QFN (QFN-44) package with exposed thermal pad. It supports output frequencies up to 1028 MHz using Skyworks' MultiSynth fractional divider technology and delivers typical phase jitter of 90 fs (12 kHz to 20 MHz) for high-performance timing applications. What is a clock generator? A clock generator is an integrated circuit that produces one or more reference timing signals used to synchronize digital logic, serializers/deserializers, analog-to-digital converters, and digital-to-analog converters within a system. Clock generators sit higher in the timing hierarchy than simple oscillators because they accept a low-frequency reference (crystal or LVCMOS) and synthesize multiple independent output frequencies through fractional-N and integer-N phase-locked loops (PLLs). High-performance variants such as the Si5340A target jitter-sensitive applications like 100G/400G optical modules, broadcast video, and wireless baseband where sub-100 fs RMS jitter is mandatory. The SI5340A-B05364-GM supports up to 4 differential or LVCMOS outputs, 4 reference inputs, and provides both integer and fractional frequency synthesis modes for sub-Hz resolution. It operates from a 1.8V core supply and 3.3V I/O supply with typical quiescent current in the 200-300 mA range. The part integrates internal LDOs, non-volatile EEPROM for stand-alone configuration, and Skyworks' ClockBuilder Pro software for register map generation. Typical applications include 10G/25G/100G Ethernet PHY clocking, FPGA transceiver reference clocks, audio/video broadcast reference timing, and wireless infrastructure baseband DSP clocks. The 44-pin QFN package provides an exposed pad for thermal dissipation at high MultiSynth update rates. Designers should use Skyworks' ClockBuilder Pro to generate the configuration header before EEPROM programming, and verify the I2C/SPI serial interface pinout against the latest Si5341/40 Rev D datasheet family reference manual. Decoupling on VDD and VDDA must use low-ESR ceramic capacitors placed within 3 mm of the supply pins. This page synthesizes distributor pricing, drop-in alternatives from the same Skyworks Si5340/Si5341 family, and practical design notes not consolidated in the manufacturer datasheet. Pricing reflects distributor breaks as of 2026-10-10 and is subject to change.
SI5340A-D-GM - 1028 MHz Ultra-Low Jitter 4-Output Clock Gen | Skyworks
The Skyworks (formerly Silicon Labs) SI5340A-D-GM is an ultra-low-jitter, any-frequency, any-output clock generator that synthesizes up to four differential or single-ended clocks up to 1028 MHz from a single reference input. Housed in a 44-pin 7x7 mm QFN package with exposed pad, the device combines a wide-band PLL with proprietary MultiSynth fractional divider technology to deliver 0.09 ps RMS phase jitter (12 kHz to 20 MHz) while consuming roughly 300 mW from a 1.71 V to 3.47 V supply. The -D ordering code denotes the 4-output variant of the Si5340 family (the Si5341 ships with 10 outputs). A clock generator is a mixed-signal IC that takes one or more reference clocks and produces one or more output clocks at arbitrary frequencies, often with finer frequency resolution than integer PLLs. In the timing hierarchy, the Si5340A sits above fixed-frequency crystal oscillators and below application-specific clock trees - it provides the low-jitter, programmable fan-out that backplanes, FPGAs, SoCs, and high-speed data converters require. MultiSynth technology performs integer and fractional frequency synthesis simultaneously, allowing non-integer output-to-input ratios without the spurious sidebands of classical fractional-N PLLs. Key features of the Si5340A-D-GM include four reference inputs (LOS) for hitless switching and holdover, per-output frequency and format programming, an I2C/SPI control port, and integrated LDOs that allow direct operation from a single 1.8 V, 2.5 V, or 3.3 V rail. The device supports LVPECL, LVDS, HCSL, CMOS, and CML output formats with per-output swing and termination control. Internal non-volatile memory stores the default frequency plan so the device boots into a known configuration without host intervention. Typical applications include 100G/400G Ethernet line cards, OTN/SONET/SDH equipment, FPGA and ASIC reference clock trees, broadcast video, test and measurement, and wireless baseband timing. The 0.09 ps jitter floor enables compliance with the strictest 25G/50G SerDes reference clock masks. When designing with the Si5340A-D-GM, follow Skyworks' CBPro clock-builder tool to generate the frequency plan and register settings; this avoids manual register tuning and guarantees datasheet jitter performance. Provide a clean 1.8 V or 2.5 V supply with adequate decoupling on each power pin and stitch the exposed paddle to a low-impedance ground plane for thermal and EMI performance. The SI5340A-D-GM is the production-programmed default-config 4-output version of the Si5340A family. Order code suffixes (e.g. -D09650) denote factory-programmed custom frequency plans; users can also program the device in-circuit over I2C. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, giving engineers a single reference for sourcing and second-sourcing the SI5340A-D-GM.
SI5340B-B-GM - 350MHz 4-Output Ultra-Low-Jitter Clock Generator
The Skyworks Solutions SI5340B-B-GM is an ultra-low-jitter, four-output clock generator with a maximum output frequency below 350 MHz, four reference inputs, and phase jitter of 0.09 ps. It is packaged in a 44-pin VFQFN with an exposed pad and uses MultiSynth technology for integer or fractional frequency synthesis. The -B suffix identifies the B-series ordering option, while -GM denotes the specified package and configuration. A clock generator is an integrated timing device that accepts one or more reference inputs and produces multiple synchronized or independently synthesized output clocks. Clock generators are part of the broader clock-and-timing IC hierarchy, alongside PLLs, dividers, buffers, jitter cleaners, and oscillators. They simplify designs requiring multiple related frequencies while reducing the number of separate clock sources and distribution components. Key features of the SI5340B-B-GM include four outputs, operation up to 350 MHz, integer and fractional synthesis modes, four reference inputs, and low phase jitter of 0.09 ps. These characteristics suit communication infrastructure, network equipment, servers, test and measurement systems, and high-speed digital systems. The product family is described by Skyworks as an ultra-low-jitter, any-frequency, any-output generator designed for exacting performance requirements. The device architecture combines clock synthesis and distribution functions, allowing multiple output frequencies to be generated from selected references. This supports clock trees that require deterministic phase relationships and low noise. A 350 MHz maximum output enables the part to address high-speed interfaces and processor-related timing needs, although the actual usable frequency depends on configuration, reference input, output divider settings, and device specifications. Typical applications include networking and telecom line cards, data-conversion systems, optical transport equipment, FPGA clock trees, server timing, and high-end instrumentation. For these systems, the 0.09 ps phase-jitter figure can help preserve timing margin where reference-clock quality and downstream receiver requirements are stringent. The four-output architecture also allows clock distribution to multiple circuit blocks without using four unrelated oscillators. PCB design should preserve short, controlled-impedance clock routes, provide clean return paths, and keep sensitive clock inputs away from noisy power and switching nodes. The exposed thermal pad requires proper thermal design and a low-impedance connection to ground. Decoupling and layout recommendations must be confirmed against the current manufacturer datasheet and reference design. This page consolidates the verified manufacturer and distributor information, package details, application guidance, cross-reference findings, and practical engineering notes for the SI5340B-B-GM. It is intended to support clock-tree design, source comparison, procurement evaluation, and PCB implementation for timing-sensitive electronic systems.
SI5341A-B04995-GM - 10-Output Ultra-Low Jitter Clock Generator | Skyworks
The Skyworks SI5341A-B04995-GM is an ultra-low jitter, any-frequency, any-output clock generator providing up to 10 differential or CMOS output clocks with output frequencies below 1028 MHz, housed in a 64-pin QFN exposed-pad (ePM) 9x9 mm package. Per the Si5341/40 family datasheet, this -B derivative integrates a custom frequency plan for the SI5341A-B04995-GM (a factory-programmed base part with a 49.495 MHz related reference plan) and supports up to 4 reference inputs with input frequencies from 10 MHz to 750 MHz. A clock generator (also called a frequency synthesizer) is a timing IC that takes one or more low-jitter reference clocks and produces multiple independent output frequencies locked to those references. Clock generators sit in the timing hierarchy between reference oscillators (e.g., OCXO, TCXO, crystal) and downstream transceivers, ADCs, DACs, FPGAs and ASICs. Within the broader IC taxonomy, this part is a Clock/Timing IC, sub-category Clock Generator, PLL, Frequency Synthesizer, and is used wherever system-level jitter budget, channel-to-channel skew, and deterministic phase noise matter. Key differentiating specifications include 0.09 ps RMS phase jitter (12 kHz to 20 MHz, typical) per Skyworks product page, integer and fractional-N synthesis modes, independently configurable output formats (LVDS, LVPECL, HCSL, CMOS, CML), and per-output programmable dividers. The Si5341A family supports hitless input switching and holdover modes for redundant reference architectures used in synchronous Ethernet and OTN equipment. The architecture combines a MultiSynth fractional-N output stage with a high-frequency low-noise PLL, giving sub-ps jitter independent of output frequency choice. The -B04995-GM suffix encodes a factory-configured frequency plan that targets specific application reference trees; users with a different plan order the same -A or -D base part and re-program the NVM through ClockBuilder Pro. Typical applications include 100G/400G optical transport networking line cards, wireless base station radios, broadcast video routers, and FPGA/ASIC reference clocking on test and measurement platforms. Designers pair the Si5341A with Skyworks Si538x jitter cleaners or Si560x oscillators when an external reference is required. When designing with this part, allocate the exposed pad (ePM) for thermal and ground return paths, route differential outputs with 100-ohm controlled impedance, and program the device through ClockBuilder Pro to lock in the required frequency plan. Holdover and reference switching behavior must be validated against system-level MTIE/TEK masks.
SI5341A-D-GM - 10-Output Any-Frequency Clock Generator | Skyworks
The Skyworks SI5341A-D-GM is a 10-output, any-frequency, any-output ultra-low jitter clock generator that synthesizes up to 1028 MHz on each of ten differential outputs, integrated in a 64-pin VFQFN (QFN) exposed-pad package. The device integrates a wide-band PLL front-end with proprietary MultiSynth fractional-divider technology to generate non-integer related frequencies with 0.09 ps RMS phase jitter (12 kHz to 20 MHz), making it one of the lowest-jitter clock ICs in its class. The Si5341A operates from 1.71 V to 3.47 V supply rails and accepts four reference inputs (LVCMOS, LVDS, LVPECL, HCSL). Outputs are independently configurable as LVDS, LVPECL, HCSL, LVCMOS, or SiLabs' proprietary format on a per-pin basis, and each output frequency is set independently in software via ClockBuilder Pro. A clock generator is a precision timing IC that accepts one or more low-frequency references (crystal, XO, or recovered clock) and synthesizes multiple clean, independent high-frequency output clocks for SoCs, FPGAs, ASICs, ADCs, DACs, and PHYs. The "any-frequency, any-output" architecture means each of the 10 outputs can be a different frequency and a different format without external loop filters, so a single Si5341A replaces multiple XO/VCXO parts. Key features include 0.09 ps RMS typical phase jitter, fractional-N synthesis (1 ppb resolution), independent per-output dividers, programmable output slew rates, output enable/format pins, hardware configuration via I2C/SPI, and field-upgradeable NVM. Hardware configurations are stored in on-chip non-volatile memory and applied at power-up, allowing fully autonomous boot without host intervention. The QFN-64 with exposed thermal pad provides thermal resistance suitable for the 1 W typical operating dissipation. The architecture combines a low-noise integer PLL reference path with MultiSynth fractional output stages that suppress fractional spurs below -75 dBc even at non-integer frequency plans. This enables clean clock trees in systems where reference and backplane frequencies are unrelated (100G/400G Ethernet, OTN, wireless baseband, JESD204B ADC/DAC clocks). Typical applications include 100G/200G/400G Ethernet switch and router timing, OTN/WDM optical transport clock generation, JESD204B/C SYSREF for high-speed ADC and DAC converters, FPGA and ASIC reference clock trees, wireless base-station fronthaul, and broadcast video reference distribution. The wide output frequency range (0.0001 MHz to 1028 MHz) covers virtually any timing requirement in modern high-speed serial systems. Each output supports independent format and frequency, so a single Si5341A can supply SYSREF, device clock, and reference clock to a JESD204B subsystem simultaneously while also driving a backplane SerDes at a different rate. This consolidation replaces a rack of XO crystals and fanout buffers and reduces BOM cost. When designing with the Si5341A, use Skyworks ClockBuilder Pro for prototype configuration and always order factory pre-programmed OPN variants (e.g., Si5341A-Dxxxx-GM) for production to lock the configuration as a one-time programmable NVM image.
SI5341A-D07228-GM - 10-Output Ultra-Low Jitter Clock Gen | Skyworks
The Skyworks SI5341A-D07228-GM is a 10-output, any-frequency, any-output ultra-low-jitter clock generator housed in a 64-pin VFQFN exposed-pad (QFN-64) package. It provides up to 1.028 GHz output frequency per channel with industry-leading 90 fs RMS phase jitter (12 kHz–20 MHz), combining a wide-band PLL with proprietary MultiSynth fractional-N synthesizer technology. According to the Si5341/40 family reference manual, the part supports external crystal inputs from 25 to 54 MHz, differential clock inputs from 10 to 750 MHz, and LVCMOS clock inputs from 10 to 250 MHz. The device operates from a 1.71 V to 3.47 V supply and is configured through an I2C/SPI interface. An any-frequency, any-output clock generator is a programmable timing IC that synthesizes arbitrary integer and non-integer related frequencies from a single reference. It belongs to the clock generator hierarchy: clock generator -> PLL/synthesizer -> timing IC -> semiconductor. By replacing multiple crystal oscillators with one programmable device, it enables design flexibility, BOM consolidation, and reduced board area for complex multi-clock systems used in communications infrastructure, broadcast video, and high-speed data conversion. Key features include 90 fs RMS ultra-low jitter, ten independently programmable outputs, integrated MultiSynth fractional-N blocks, and built-in holdover capability. The Si5341A-D07228-GM operates from a 1.71 V to 3.47 V supply, offers selectable LVDS, LVPECL, HCSL, and LVCMOS output formats, and integrates an EEPROM for autonomous configuration. It supports Glitchless output muting and per-output phase adjustment, which simplifies PCB layout in dense multi-clock domains. Architecturally, the Si5341A-D07228-GM combines a wide-band integer PLL that locks to an external reference with up to five MultiSynth fractional divider blocks that each independently synthesize non-integer related output frequencies. This dual-stage architecture avoids the spurs typical of single-loop fractional-N synthesizers while keeping frequency flexibility. Register-only configuration uses an I2C or SPI serial interface, and optional non-volatile configuration via on-chip EEPROM allows standalone boot without a host controller. Typical applications include wireless base station timing, broadcast video reference clock generation, high-speed ADC/DAC sampling clocks, FPGA/ASIC reference and fabric clocks, OTN/SONET/SDH line cards, and server/storage timing. In all these roles, the Si5341A's 90 fs jitter preserves signal integrity in high-speed serial links and tight SNR budgets. When designing with this device, allocate a 64-pin 9 mm × 9 mm QFN footprint with a sufficient thermal via array under the exposed pad to keep junction temperature within range. A high-isolation multi-layer stack-up with split analog/digital ground is recommended because the part is sensitive to power-supply noise on the PLL supply rails. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes that are not found in the manufacturer datasheet alone.
SI5341B-B-GM - 350MHz 10-Output Clock Generator | Skyworks
Skyworks Solutions SI5341B-B-GM is an ultra-low-jitter, any-frequency clock generator with 10 differential outputs, a maximum output frequency of 350 MHz, and a 64-pin VFQFN exposed-pad package. The family accepts references up to 750 MHz and uses integer or fractional frequency synthesis to generate independent output frequencies. According to the verified product information, its phase jitter is 0.09 ps. A clock generator is a timing IC that converts one or more reference sources into multiple synchronized or independently synthesized clocks. The Si5341B belongs to the PLL clock-generator hierarchy: clock generator -> frequency synthesizer -> timing and clock-management IC. This architecture reduces the number of separate oscillators and distribution components required in communications, networking, industrial, and test systems. Principal features include 10 outputs, four reference inputs, integer and fractional synthesis modes, a 350 MHz maximum output, and 0.09 ps phase jitter. A search listing for the target order code also identifies a 1.71 V to 1.89 V supply range, while Arrow describes a 10 MHz to 750 MHz input and 350 MHz output range. These values make the device suitable for systems requiring multiple low-jitter clocks with flexible frequency relationships. Internally, the Si5341B family combines a wide-band phase-locked loop with MultiSynth fractional-synthesis technology. Integer and fractional modes allow designers to select clock frequencies that are integer- or non-integer-related to the references. Differential outputs can support high-speed links and clock-sensitive circuitry, while the fractional capability simplifies synthesis when a conventional integer divider cannot produce the required relationship. Typical uses include high-speed serial-interface clocking, optical transport modules, network equipment, industrial instrumentation, and semiconductor test systems. The 0.09 ps phase-jitter figure is particularly relevant where timing margin, data-eye closure, or reference-clock purity affects system performance. Engineers must still evaluate frequency-plan support, output logic levels, reference stability, and PCB thermal conditions for each specific configuration. For layout, place the exposed-pad connection and decoupling network exactly as directed by the manufacturer reference manual. The VFQFN package relies heavily on its thermal pad for heat spreading, so via stitching and uninterrupted ground or supply copper beneath the device are important. This page combines verified source data with explicitly marked data gaps rather than inferring unverified electrical limits. This product data adds practical interpretation of verified distributor pricing, package identity, family-level frequency synthesis, and replacement constraints. It distinguishes an orderable configuration from other Si5341B programming variants and avoids treating different frequency codes as unqualified drop-in replacements.
SI5341B-B05471-GM - 10-Output Ultra-Low-Jitter Clock Generator | Skyworks
The Skyworks Solutions (formerly Silicon Labs) SI5341B-B05471-GM is an ultra-low-jitter, 10-output, any-frequency (< 350 MHz) clock generator housed in a 64-pin VFQFN exposed-pad package. The device delivers 0.09 ps typical RMS phase jitter (12 kHz to 20 MHz integration band), four reference inputs, and supports both integer and fractional-N frequency synthesis modes for flexible timing architectures in high-performance systems. A clock generator is a semiconductor device that produces one or more precisely timed reference signals used to synchronize digital logic, converters, serializers, and RF front-ends. Within the broader hierarchy, the SI5341B-B05471-GM is a PLL-based frequency synthesizer that belongs to the clock generator family, itself a sub-category of clock & timing ICs in the power management / signal chain ecosystem. Unlike simple crystal oscillators, multi-output clock generators like the Si5341B consolidate what would otherwise require multiple discrete XOs and fanout buffers into a single IC configurable via I2C/SPI, simplifying BOM and improving timing margin across PCB regions. Key features include 0.09 ps RMS phase jitter, 4 reference inputs (differential or single-ended), 10 output drivers (selectable LVDS/LVPECL/HCSL/CMOS), an on-chip fractional-N PLL with MultiSynth technology, and a per-output integer divider. The device supports output frequencies from < 1 Hz up to 350 MHz on any output, with independent frequency and format programming. The integrated XTAL oscillator accepts a 25 MHz to 54 MHz fundamental-mode resonator for smooth frequency and format programming. The Si5341B architecture combines a low-noise MultiSynth fractional divider stage with a high-frequency VCO, achieving jitter performance that previously required discrete VCXOs plus custom ASICs. ClockBuilder Pro software generates the register map that initializes the device, removing manual I2C programming and reducing firmware development time. Typical applications include 100G/400G optical transport, OTN/SONET/SDH line cards, broadcast video reference timing, wireless baseband and digital front-end (DFE) clocking, enterprise switch/router timing, and FPGA/ASIC reference clock distribution. Any application requiring multiple low-jitter, format-flexible clocks from a single reference benefits from the Si5341B. When designing with this part, use the ClockBuilder Pro GUI to generate the device profile - register map, frequency plan, and pin configuration - and avoid manual programming. Layout must follow Skyworks application note AN862 (jitter optimization) to minimize output-to-output crosstalk and power-supply noise coupling. This page aggregates Skyworks-published specs, distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone - giving a holistic view for BOM decisions.
SI5341B-D07870-GMR - 10-Out 350MHz Jitter Clock Gen | Skyworks
The Skyworks Solutions SI5341B-D07870-GMR is an ultra-low-jitter, 10-output, any-frequency clock generator housed in a 64-pin VFQFN (Quad Flat No-Lead) package with exposed pad, supporting output frequencies up to 350 MHz. Built on MultiSynth fractional synthesis technology, it provides 0.09 ps RMS phase jitter performance across the entire operating range and accepts up to 750 MHz input reference. The -D07870- suffix indicates a factory-preprogrammed frequency plan (custom NVM configuration) for a specific customer design, packaged on Tape & Reel per the -GMR suffix. A clock generator is a timing IC that synthesizes one or more precise output frequencies from a single reference input, eliminating the need for multiple crystal oscillators in a system. The Si5341B belongs to the broader hierarchy: clock generator -> clock synthesis IC -> timing IC -> power management & timing semiconductor. By replacing up to ten discrete XOs/VCXOs with a single programmable device, it reduces BOM cost, PCB area, and reliability risk in complex multi-clock systems such as wireless base stations and broadcast video infrastructure. Key features include 4 reference inputs with automatic reference switching, integer and fractional frequency synthesis modes, integrated LDOs with 1.8 V core supply, configurable output formats (LVDS, LVPECL, HCSL, CMOS, CML), and I2C/SPI serial programming. Independent output dividers per channel and 0.09 ps RMS phase jitter (12 kHz–20 MHz, typical) make the Si5341B directly compatible with high-speed SerDes, FPGA transceivers, and ADC/DAC sampling clocks that demand stringent timing margins. Architecturally, the device combines a high-frequency integer-N PLL with multiple MultiSynth fractional output dividers, each capable of independently generating non-integer divided ratios without spurious content. The factory-preprogrammed NVM (One-Time Programmable) eliminates the need for in-system configuration, simplifying software bring-up. Per the Skyworks datasheet, the device operates from a 3.3 V core supply with 1.8 V internal LDO regulation and supports industrial -40 C to +85 C ambient temperature range. Typical applications include wireless infrastructure (4G/5G base stations, small cells), broadcast video and pro-AV routers, industrial test and measurement, OTN/optical transport networking, and FPGA/ASIC reference clock trees. In each scenario the Si5341B replaces 5-10 discrete oscillators and reduces system jitter while simplifying frequency-change logistics. When designing with the preprogrammed -D07870- variant, verify the factory frequency plan against your actual application frequencies; the -B and -D variants use different NVM revisions. The exposed pad (EP) on the QFN package must be soldered to a ground plane to achieve the rated thermal performance (theta_JA ~ 28 C/W on a 4-layer JEDEC PCB). This page synthesizes distributor pricing, drop-in alternatives, and practical design notes drawn from the Skyworks Si5341B datasheet, the Si5341/40 Family Reference Manual, and authorized distributor listings as of 2026-10-10. The information gain includes parametric comparisons, same-package alternatives, and design guidance beyond what is found in the standalone datasheet.
SI5341B-D08976-GM - 10-Output Ultra-Low Jitter Clock Generator | Skyworks
The Skyworks (formerly Silicon Labs) SI5341B-D08976-GM is an ultra-low jitter, 10-output, any-frequency (<350 MHz) any-output clock generator housed in a 64-pin VQFN exposed-pad package. It generates any combination of output frequencies from any input frequency with 90 fs RMS typical jitter performance, making it suitable for high-performance timing applications where signal integrity is critical. What is a clock generator? A clock generator is a timing integrated circuit that synthesizes one or more output clock signals from one or more reference inputs (crystal, LVCMOS, or differential clock). Clock generators belong to the clock and timing IC family within the broader power management and signal chain hierarchy, and they are foundational building blocks in nearly every digital system. The SI5341B family specifically targets ultra-low jitter applications such as 100G/400G optical modules, broadband communications, and high-speed data converters, where phase noise directly limits bit-error-rate and signal-to-noise ratio. The SI5341B supports input frequency ranges of 25 to 54 MHz from an external crystal, 10 to 750 MHz from a differential clock, and 10 to 250 MHz from an LVCMOS clock. It provides both integer and fractional frequency synthesis modes, four reference inputs, and 10 configurable outputs. Phase jitter is rated at 0.09 ps RMS, a figure that places it among the lowest-jitter clock generators in its class and enables compliance with the most stringent telecom and datacom standards such as OTU/STM-64, PCIe Gen 5, and 56G/112G SerDes reference clock requirements. Architecturally, the SI5341B integrates a MultiSynth fractional divider engine, a low-noise PLL with integrated VCO, and per-output divider and driver stages. The device is configured through I2C/SPI with a graphical ClockBuilder Pro software tool that simplifies register programming. Outputs can be independently configured as LVDS, LVPECL, HCSL, CML, or LVCMOS, allowing direct connection to serializers, FPGAs, ASICs, and DACs without external level translation. Typical applications include wired networking (switches, routers, line cards), optical transport (OTN/SONET/SDH), wireless base stations, broadcast video, test and measurement equipment, and high-performance FPGA/ASIC reference clock trees. In each of these, the SI5341B replaces multiple fixed-frequency oscillators and PLL devices with a single programmable part, simplifying BOM and improving frequency agility across product variants. When designing with the SI5341B, ensure the exposed pad is soldered to a sufficient ground plane for thermal dissipation and noise isolation. Place decoupling capacitors as close as possible to the supply pins and follow Skyworks application note AN862 for jitter optimization in next-generation internet infrastructure systems. Output format, drive strength, and frequency for each of the 10 outputs should be configured via ClockBuilder Pro before register loading. This page synthesizes distributor pricing, drop-in alternatives within the Si534x family, and practical design notes not found in the manufacturer datasheet summary, providing engineers with a single-source reference for evaluation and procurement decisions.
SI5341B-D11825-GMR - 10-Output Clock Generator | Skyworks
The Skyworks SI5341B-D11825-GMR is an ultra-low-jitter, 10-output, any-frequency (less than 350 MHz), any-output clock generator IC housed in a 64-pin VFQFN (QFN) exposed-pad package. Per the Skyworks Si5341/40 Rev D family reference manual, the Si5341B uses MultiSynth fractional divider technology to synthesize independent output frequencies on each of its ten outputs, making it well suited for systems that require multiple unrelated clock domains from a single reference. A clock generator (also called a frequency synthesizer or clock synthesizer) is a category of timing integrated circuit that takes one or more reference inputs and produces one or more output clocks at independently programmed frequencies. Within the broader timing hierarchy, clock generators sit below crystal oscillators and above clock buffers: they live in the power-management-and-timing section of mixed-signal designs, often classified as a Clock & Timing IC. The Si5341B family is engineered for the upper end of this category, where output jitter in the femtosecond range and multi-domain frequency flexibility are both required. Key features include 10 independently configurable output channels, sub-200 fs RMS typical output jitter, integer and fractional frequency synthesis on every output, an I2C/SPI control interface, an integrated crystal input stage, and support for output frequencies up to 350 MHz on each channel. The 64-VFQFN exposed-pad package provides a low thermal resistance path, allowing full operation across the -40C to +85C industrial temperature range. The Si5341B-D11825-GMR is a factory-pre-programmed derivative of the Si5341B-D-GMR base part, where the -D11825- suffix denotes the customer-specific frequency plan pre-loaded into the part's non-volatile memory. Designers order this derivative to receive a device that is pre-configured for a specific set of output frequencies without having to program the device over I2C/SPI at first power-up, simplifying firmware bring-up and eliminating register-initialization risk. Typical applications include high-performance wireless baseband cards, optical transport networking line cards, FPGA-SoC reference clocking for high-speed transceivers, broadcast video and imaging systems, and industrial test-and-measurement equipment. The wide frequency range and low jitter make it suitable as the master timing source for systems that also require jitter-cleaner behavior when paired with an external jitter attenuator such as the Si5342A. When designing with this device, observe the Skyworks reference manual recommendation to use the ClockBuilder Pro software to generate the configuration header, place a 1 uF decoupling capacitor close to each of the multiple supply pins, and bond the central exposed pad (EP) to a continuous low-impedance ground plane for thermal dissipation. This page synthesizes distributor pricing, drop-in alternatives drawn from the same Skyworks Si5341B family, and practical design notes that go beyond what the manufacturer datasheet publishes as a standalone PDF.
SI5341B-D13308-GM - 10-Output Ultra-Low Jitter Clock Generator | Skyworks
The Skyworks SI5341B-D13308-GM is a 10-output, any-frequency (< 350 MHz), any-output ultra-low-jitter clock generator housed in a 64-pin QFN package with exposed pad. The device delivers 0.09 ps RMS phase jitter (12 kHz to 20 MHz, typical) using MultiSynth fractional dividers, four reference inputs, and configurable output formats (LVDS, LVPECL, LVCMOS, HCSL). It operates from a 1.8 V / 3.3 V core supply and supports I2C/SPI host configuration via Skyworks ClockBuilder Pro. A clock generator is a mixed-signal PLL-based IC that synthesizes one or more precise output frequencies from one or more reference inputs, providing clean timing for downstream digital, analog, and RF subsystems. Within the broader hierarchy, the SI5341B is a clock generator -> PLL/ frequency synthesizer -> timing IC -> power management & timing -> semiconductor. The device replaces multiple crystal oscillators and discrete PLLs in designs that require many frequency-related outputs at low jitter, reducing BOM count and PCB area. Key features of the SI5341B include 10 differential/CMOS outputs, integer and fractional frequency synthesis modes, output frequencies up to 350 MHz, programmable output swing and slew rate, per-output enable/disable, loss-of-reference and loss-of-lock indicators, and an internal EEPROM for autonomous power-up configuration. The chip integrates two MultiSynth blocks to deliver non-related output frequencies from a single reference. The architecture combines a high-frequency fractional-N PLL with a divider chain based on Skyworks' MultiSynth technology, which produces lower fractional spurs than classic fractional-N designs and supports frequency increments of 1 Hz to satisfy SONET/SDH, Ethernet, PCIe, and JESD204B clocking requirements. Status monitoring is provided through interrupt flags, GPIO pins, and an SMBus alert line. Typical applications include wireless base-station transceivers, OTN/framer line cards, broadcast video equipment, FPGA/SoC reference clocks, and instrumentation that demands deterministic low-jitter timing rails. The wide format support also makes it suitable for replacing legacy crystal/oscillator stacks. Designers should note that PCB layout for the 64-QFN package benefits from a solid ground/power pour under the exposed pad (EP) for thermal dissipation and return-path integrity; the EP must be soldered to a stitched ground plane to meet the datasheet jitter specification. Use ClockBuilder Pro to generate the register map; manual register programming is not recommended. This page synthesizes distributor pricing, drop-in same-package variants, and practical design notes not found in the manufacturer datasheet alone.
SI5344B-D-GM - 4-Output Jitter Attenuator, 350 MHz | Skyworks
The Skyworks Solutions SI5344B-D-GM is a 4-output, any-frequency, any-output jitter attenuator and clock multiplier that operates up to 350 MHz output frequency, housed in a 44-pin QFN (7x7 mm) package with exposed thermal pad. It supports an input frequency range of 0.008 MHz to 750 MHz and provides up to 4 differential or single-ended output clocks with sub-100 femtosecond RMS jitter, enabled by the fourth-generation DSPLL and MultiSynth fractional-N technologies integrated on-chip. A jitter attenuator is a clock-tree building block whose job is to take a noisy reference clock and synthesize a clean, low-jitter output clock while rejecting upstream phase noise. Within the broader clock-tree taxonomy, jitter attenuators sit between simple clock buffers (no frequency synthesis, no jitter cleaning) and full frequency synthesizers. The Si5344 series from Skyworks targets the highest tier of jitter performance for communications infrastructure, broadcast video, and high-speed data-conversion systems. Key features include four independently configurable output dividers with output frequencies up to 350 MHz, integrated XTAL reference input compensation, programmable jitter attenuation bandwidth, and in-circuit programmable non-volatile memory that guarantees a known frequency at every power-up. The on-chip MultiSynth block enables non-integer frequency translations, so designers are not constrained to integer ratios when generating system clocks from a single reference. Typical applications include 10G/25G/100G Ethernet line cards, OTU/SONET/SDH transport equipment, OTN multiplexers, FPGA and ASIC reference clock generation, professional broadcast video formats, and high-performance data-converter clocking where reference jitter directly limits achievable SNR. When designing with this device, configure the outputs, dividers, and jitter-attenuation bandwidth through the Skyworks ClockBuilder Pro software, which exports a complete register map and a project-specific NVM image that guarantees deterministic startup behavior.
SI5345A-D-GM - 10-Output Jitter Attenuator, <1028 MHz | Skyworks
The Skyworks SI5345A-D-GM is a 10-channel, any-frequency, any-output jitter attenuator and clock multiplier housed in a 64-pin VFQFN exposed-pad (QFN-64 EP) package. It accepts an input frequency range from 8 kHz to 750 MHz (differential) or 8 kHz to 250 MHz (LVCMOS) and generates any output frequency from 100 Hz up to 1028 MHz (differential), with ultra-low jitter of 90 fs RMS typical. The DSPLL-based architecture supports digitally programmable jitter attenuation bandwidth so that jitter performance can be optimized for each application. A jitter attenuator is a clock IC that cleans up timing noise from an upstream reference or recovered clock and re-generates a low-jitter output clock for downstream serializers, ADCs, DACs, FPGAs, ASICs, and network PHYs. In the clock-tree hierarchy it sits between a primary reference (XO, OCXO, or recovered clock) and the fan-out clock generators/buffers that feed individual MAC, framer, or transceiver blocks, falling under the broader categories of clock synthesis IC, timing IC, and PLL frequency synthesizer. The SI5345 family includes Si5345A, Si5345B, Si5345C, and Si5345D variants, all pin-compatible and supported by the ClockBuilder Pro configuration software. The '-D' order code suffix indicates an unprogrammed (blank/prototype) device that ships with default registers and is configured in-circuit via I2C/SPI, while the 'A' revision defines which PLL and synthesizer block layout is used. The 64-QFN exposed-pad package and integrated LDOs simplify board layout, while digital holdover with external crystal support (25 to 54 MHz on XA/XB) maintains frequency accuracy when the input reference is lost. Typical applications include 100G/400G Ethernet line cards, OTN/optical transport framer clocks, OTU/OTN timing, Synchronous Ethernet (SyncE) and IEEE 1588 PTP node clocks, wireless base-station JESD204B/C clocking, FPGA/ASIC transceivers, and broadcast video reference timing. The 90 fs RMS jitter floor is more than adequate for 56G/112G SerDes, 25G/50G Ethernet PHYs, and high-speed ADC/DAC sampling clocks. When designing with this part, place the 64-QFN exposed pad over a continuous ground plane with at least four thermal vias to the inner ground layer for lowest theta-JA. Decouple each supply pin (VDD, VDDA, VDDO) with a 100 nF X7R placed within 2 mm of the pad, and follow the ClockBuilder Pro project for register defaults. Holdover stability depends on the external XA/XB crystal; an OCXO reference is preferred for telecom-grade holdover performance. This page synthesizes distributor pricing, pin-compatible same-family drop-ins, and PCB-layout design notes that complement the manufacturer datasheet and ClockBuilder Pro reference manual, giving engineers an at-a-glance comparison set not found on a single source page.
SI5345A-D04313-GM - 10-Output Jitter Attenuator Clock | Skyworks
The Skyworks (formerly Silicon Labs) SI5345A-D04313-GM is a factory-preprogrammed, low-jitter, 10-output, any-frequency (< 1028 MHz) jitter attenuator / clock multiplier housed in a 64-pin VFQFN (9x9 mm) exposed-pad package. It is a custom-configured variant of the Si5345A Rev. D family, delivered with a unique frequency plan defined by the five-digit suffix "D04313" generated by ClockBuilder Pro software. A jitter attenuator is a specialized clock generator / PLL device that cleans up jitter and phase noise from a reference clock and produces multiple low-jitter output frequencies simultaneously. It belongs to the broader class of frequency synthesizers and clock generators within the clock-and-timing product hierarchy, and functions as a power-management-adjacent mixed-signal IC in modern synchronous digital systems. Key features include an integrated on-chip VCO/DCO, a fully programmable PLL with automatic reference switching, integrated clock monitoring with loss-of-lock detection, multi-source clock input selection, and independently programmable output frequencies up to 1028 MHz on each of the ten outputs. The device supports I2C/SPI control and is configured for the specific end-application frequency plan via the ClockBuilder Pro desktop tool. Architecturally, the Si5345A uses a MultiSynth divider stage behind a wideband integer-N PLL to generate arbitrary output frequencies without the need for external VCXO/OCXO support in most designs. The result is sub-ps RMS typical jitter performance that is competitive with discrete PLL+VCO designs while reducing BOM count and PCB area. Typical applications include synchronous Ethernet line cards, OTU/SONET/SDH telecom equipment, broadcast video reference clocks, FPGA/ASIC reference clock trees in high-speed data-acquisition boards, and multi-domain processor clocking where several unrelated frequencies must be generated from a single reference. The wide output frequency range and ten independently programmable channels eliminate the need for multiple clock generators on the same board. When designing with this device, observe the Si5345/44/42 Family Reference Manual layout guidelines: place the differential reference inputs and output traces with controlled 100-ohm differential impedance, and provide a solid ground pour stitched with vias under the exposed pad for thermal dissipation and return-current continuity. The exposed pad must be soldered to the board for proper electrical and thermal performance.
SI5345A-D04594-GM - 10-Output Jitter Attenuator | Skyworks
The Skyworks (formerly Silicon Labs) SI5345A-D04594-GM is a 10-channel, any-frequency, any-output jitter attenuator and clock multiplier serving as a high-performance timing reference for communications infrastructure, broadcast video, and professional audio systems. The device integrates a MultiSynth fractional-N divider array that independently synthesizes up to 10 differential or single-ended clocks from a single reference input, with maximum output frequency of 1.028 GHz and sub-200 femtosecond typical RMS jitter. The custom configuration code (-D04594-) defines a factory- or user-programmed frequency plan optimized for the target application. A clock synthesizer / jitter attenuator is a timing integrated circuit that takes a single reference input (crystal, oscillator, or recovered clock) and produces multiple low-jitter output frequencies. These devices sit in the timing-tree hierarchy: clock IC -> clock generator -> frequency synthesizer -> PLL (phase-locked loop). They are commonly used in place of multiple crystal oscillators and PLLs to reduce board area, BOM cost, and EMI leakage. Key features of this Si5345 variant include 10 independently configurable outputs, per-output frequency synthesis up to 1.028 GHz, programmable output formats (LVDS, LVPECL, HCSL, CMOS, CML), digital jitter attenuation bandwidth programming via ClockBuilder Pro, and independent output enable / frequency scaling registers. The 64-pin QFN exposed-pad package provides a low thermal resistance path to the PCB ground plane. Internally the Si5345 uses two-stage MultiSynth architecture: a low-jitter integer-N PLL locks to the reference, then each output passes through a fractional-N divider that synthesizes arbitrary rational frequency ratios. Loop bandwidth is digitally programmable (typical 0.1 Hz to 1 kHz) for optimized jitter transfer in PLL cleanup, SONET/SDH, or OTN applications. Typical applications include wireless base-station timing, OTU/SONET line cards, broadcast SDI/HD-SDI reference clocks, FPGA / ASIC SerDes reference inputs, and high-end professional audio clocks. The 1.7 V to 3.47 V core supply and 1.8 V / 3.3 V IO supplies allow direct interface to most modern FPGAs, SoCs, and ASICs without level translation. When designing with this part, configure the device once using ClockBuilder Pro, then export the resulting register file and NVM image for production programming. Maintain a clean PCB ground return under the exposed pad and follow the Skyworks Si5345 Reference Manual layout recommendations.
SI5345A-D04594-GMR - 10-Output Jitter Attenuator | Skyworks
The Skyworks Solutions (formerly Silicon Labs) SI5345A-D04594-GMR is a factory-programmed 10-output, any-frequency (< 1028 MHz) jitter attenuator clock IC housed in a 64-pin QFN-EP (9x9 mm) package with exposed thermal pad. The Si5345 family uses a fourth-generation MultiSynth divider technology and a low-jitter VCO to deliver industry-leading phase noise and sub-200 fs RMS jitter while supporting frequencies up to 1028 MHz on each of its ten differential or single-ended outputs. A clock synthesizer (sometimes called a clock generator or frequency synthesizer) is an IC that derives one or more precise output frequencies from a single reference source. Within the broader hierarchy, the SI5345A belongs to the clock timing IC family, which sits under integrated circuits and plays a critical role in synchronous digital systems: SOC > integrated circuit > clock & timing IC > clock generator > frequency synthesizer > jitter attenuator. Jitter attenuators add a low-bandwidth PLL on top of a synthesizer to filter reference-clock noise before redistribution to downstream PHYs, ADCs, DACs, and FPGAs. Key features of this variant include ten independently configurable output formats (LVDS, LVPECL, HCSL, CML, CMOS, HSTL, SSTL), an I2C control interface, 1.71 V to 1.89 V core supply range, and a -40 C to +85 C industrial operating range. The -D04594-GM code denotes a custom factory-programmed frequency plan generated by Skyworks ClockBuilder Pro, which removes the burden of in-system NVM programming. Architecturally, the Si5345A uses a fractional-N MultiSynth divider per output, allowing non-integer frequency translations without compromising phase noise. The internal low-jitter VCO and digitally programmable loop bandwidth enable optimization for each application's jitter transfer characteristics. This makes the SI5345A well suited to reference clock generation for 100G/400G Ethernet PHYs, OTN/SONET/SDH line cards, FPGA transceiver reference chains, wireless base-station timing, and high-end broadcast video. Typical applications include 100G/400G Ethernet switches, OTN/SONET/SDH line cards, FPGA/ASIC reference clock trees, wireless base-station timing boards, and broadcast video routers. The wide output format support and low jitter make it a flexible single-chip timing solution for mixed-signal boards that would otherwise require multiple oscillators or clock generators. When designing with the SI5345A, place the 0.1 uF + 10 uF decoupling network as close as possible to each supply pin and expose the e-pad with at least 25 thermal vias to an internal ground pour. Use the ClockBuilder Pro configuration file attached to your -D04594 order code to load the pre-configured frequency plan into the IC; do not re-program the NVM unless intentionally overriding the factory image. This page synthesizes verified distributor pricing, drop-in compatible alternatives, and practical PCB layout notes that are not aggregated on the manufacturer datasheet alone.
SI5345A-D06546-GM - 10-Output Any-Freq Jitter Attenuator | Silicon Labs
The Silicon Labs (Skyworks) SI5345A-D06546-GM is a low-jitter, 10-output, any-frequency (<1028 MHz) clock multiplier and jitter attenuator housed in a 64-pin QFN (10x10 mm) package with exposed pad. This device delivers any combination of output frequencies up to 1.028 GHz on each of its 10 differential or single-ended outputs, all synthesized from a single reference input. What is a clock multiplier/jitter attenuator? A clock multiplier is a timing-IC block that synthesizes one or more higher-frequency output clocks from a lower-frequency reference. A jitter attenuator is a PLL (phase-locked loop) that uses a narrow loop bandwidth to filter reference-clock phase noise before re-synthesizing a clean output. Together, these functions provide a low-noise, deterministic timing source for systems where the upstream reference is noisy (recovered clocks, CPLD/FPGA SERDES, PHY clocks). The SI5345A belongs to the clock generator family hierarchy: clock IC -> clock generator/jitter cleaner -> PLL-based clock multiplier -> timing IC -> analog mixed-signal IC -> semiconductor IC. Key features include a digitally programmable jitter-attenuation bandwidth for application-level optimization, sub-200 fs typical RMS jitter (12 kHz-20 MHz), integrated fractional-N PLLs with multi-mode DSPLL architecture, and I2C/SPI host control via ClockBuilder Pro software. Outputs support LVPECL, LVDS, HCSL, CML, CMOS, and SSTL signaling, eliminating the need for discrete level translators when interfacing with FPGAs, ASICs, and PHYs. Architecturally, the SI5345A uses Silicon Labs' MultiSynth technology that pairs one high-frequency DSPLL with multiple fractional dividers, allowing any output to take any frequency from 1 Hz to 1.028 MHz independently. The on-chip voltage regulators accept a single 1.8V/3.3V supply rail and generate all internal voltages, simplifying PCB power design. Typical applications include carrier-grade networking (SyncE, IEEE 1588), data-center switches/routers, OTN/optical line cards, broadcast video reference timing, GPON/PON OLT, broadband DSLAM, and 100G/200G/400G Ethernet PHY clocking. The 10 independent outputs let one device replace multiple crystals and PLLs in a typical timing tree. Design tip: route the reference input (XA/XB) and the high-frequency serial host signals (I2C/SPI/GPIO) with controlled-impedance traces and shielded ground pours to preserve the low-jitter performance; place the on-chip regulator bypass capacitors within 50 mils of the supply pins. Wideband scope probes on jitter-cleaned outputs verify compliance with the relevant jitter mask (e.g., G.8262, PCIE Gen4). This page synthesizes distributor pricing, drop-in Si5345/Si5344/Si5342 family alternatives, and practical design notes not found in any single manufacturer datasheet or distributor listing. PARAGRAPH_PLACEHOLDER_TEMP_DELETE