Integrated Circuits

ENC28J60/SS

ENC28J60/SS - 10Mbps SPI Ethernet Controller | Microchip

The Microchip Technology ENC28J60/SS is a 10 Mbps stand-alone Ethernet controller with an integrated MAC, 10BASE-T PHY, 8 KB of buffer RAM, and an SPI serial interface in a 28-pin SSOP package. It operates from a 3.1 V to 3.6 V supply and supports an industrial temperature variant family identified by the ENC28J60-I/SS ordering code. What is a stand-alone Ethernet controller? It is an Ethernet interface integrated circuit that connects a host microcontroller or processor to a physical Ethernet network. The ENC28J60/SS combines MAC and PHY functions with packet buffering, while the host communicates through SPI rather than a parallel bus. Its 10 Mbps 10BASE-T capability makes it suitable for legacy and low-bandwidth embedded networks, especially where board area and system cost are important. Key verified features include 10 Mbps Ethernet operation, integrated MAC and PHY, 8 KB of buffer RAM, SPI interface, a 28-pin SSOP package, and a 3.1 V to 3.6 V supply range. The controller is designed to reduce host-side interface complexity and can be used in systems where the connected host already has sufficient processing capacity for the required networking software. The ENC28J60/SS includes the MAC and PHY in one package, allowing an embedded system to implement Ethernet communication without a separate external Ethernet PHY. Its buffer RAM supports packet handling between the SPI host interface and the Ethernet physical layer. The manufacturer product page identifies it as a 28-pin 10BASE-T stand-alone Ethernet controller with 8 Kbytes of buffer RAM. Typical applications include embedded control systems, industrial automation equipment, data loggers, building automation controllers, network-connected sensors, and microcontroller platforms requiring 10BASE-T connectivity. The SPI interface allows the device to be paired with host controllers such as STM32, ATmega, PIC, or other embedded processors that provide the required firmware. When designing around the ENC28J60/SS, confirm the 3.1 V to 3.6 V operating supply, use the manufacturer-recommended 25 MHz parallel-resonance crystal arrangement, and provide the required magnetic-interface and Ethernet physical-layer components. Verify the exact SSOP footprint, pin assignment, thermal conditions, and host timing requirements against the manufacturer datasheet before layout release.

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ENC28J60T-I/ML

ENC28J60T-I/ML - 10BASE-T Ethernet Controller | Microchip

The Microchip Technology ENC28J60T-I/ML is a stand-alone 10BASE-T Ethernet controller with an integrated MAC and PHY, 8 KB of transmit and receive packet buffer RAM, and an SPI serial interface, housed in a 28-pin QFN package. It combines Ethernet frame handling and physical-layer networking in one device, reducing the need for a separate Ethernet PHY in embedded systems. A stand-alone Ethernet controller is an interface IC that connects a microcontroller or embedded processor to a wired Ethernet network. The ENC28J60 family provides IEEE 802.3-compatible 10BASE-T operation, hardware packet filtering, programmable receive filtering, and an SPI host interface. This product type sits within interface controllers, communication ICs, semiconductors, and the broader embedded networking hierarchy. Key features include an integrated 10BASE-T PHY, integrated Ethernet MAC, 8 KB of dual-port buffer SRAM, and a serial SPI interface. The controller is designed for space-constrained embedded equipment where a compact package and a single-network interface simplify board design. Its buffered packet architecture allows the host processor to handle Ethernet traffic without requiring a large external network-memory device. The ENC28J60T-I/ML uses a 3.3 V supply and is offered in a 28-pin QFN package with a 6 x 6 mm footprint. The manufacturer describes the ENC28J60 as a small-footprint solution intended to reduce complexity, board space, and system cost. The SPI interface also provides a straightforward connection to microcontrollers that have SPI peripherals, while the integrated PHY handles the physical 10BASE-T network connection. Typical applications include VoIP equipment, industrial automation, building automation, home control, security systems, and instrumentation. In each case, the controller can provide network connectivity to an embedded host processor without requiring a separate Ethernet MAC implementation. It is particularly useful where 10BASE-T connectivity, modest network throughput, and compact board area are more important than fast Ethernet performance. When designing around the ENC28J60T-I/ML, verify the host processor's SPI voltage and timing requirements, provide the required decoupling and Ethernet magnetics interface specified by the manufacturer, and confirm that the selected package and exposed-pad layout match the PCB footprint. Use the manufacturer datasheet's pin-description and layout tables when assigning nets and defining the physical implementation. This product page combines the manufacturer's ENC28J60 technical description, the exact ENC28J60T-I/ML package and ordering information, pricing evidence rules, and practical integration guidance for engineers evaluating embedded Ethernet designs.

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ENC28J60T-I/SO

ENC28J60T-I/SO 10BASE-T Ethernet Controller | Microchip Technology

Microchip Technology ENC28J60T-I/SO is a 28-pin stand-alone Ethernet controller with an integrated MAC and 10BASE-T PHY, an SPI serial interface, and 8 Kbytes of transmit and receive packet buffer SRAM. The device operates from a 3.3 V supply and is packaged in a 28-SOIC format. Its integrated Ethernet interface is intended for embedded systems that require a compact, low-cost network connection without a separate Ethernet transceiver or dedicated network controller. An Ethernet controller is a semiconductor that manages frame transmission, reception, buffering, packet filtering, and physical-layer signaling. The ENC28J60 family combines the functions of an Ethernet MAC, a 10BASE-T PHY, and an SPI host interface into one device. This integration reduces the number of external components required on a controller-based product while preserving a standardized communication path to the host processor. The ENC28J60T-I/SO supports IEEE 802.3-compatible Ethernet operation and provides programmable packet filtering, multicast filtering, programmable LED indication, a wake-up function, and power-on reset. Its 8 Kbytes of dual-port buffer SRAM helps the controller manage incoming and outgoing Ethernet packets while the host processor communicates over SPI. These features make the device suitable for small embedded platforms where a full-size network interface would add unnecessary board area and system complexity. Typical applications include VoIP terminals, industrial automation equipment, building automation controllers, home-control products, security systems, and instrumentation. The SPI host interface allows the device to be connected to microcontrollers and other embedded processors that can configure the Ethernet controller through registers and interrupt or polling mechanisms. The integrated PHY also simplifies the Ethernet magnetics and connector arrangement when implemented according to the manufacturer’s reference design. The 3.3 V supply requirement, 10BASE-T data rate, 28-SOIC package, and integrated MAC/PHY architecture should be checked against the host processor’s I/O voltage, SPI timing, Ethernet magnetics, and isolation requirements. Because the Ethernet controller includes sensitive analog and digital functions, follow the manufacturer’s recommended decoupling, grounding, trace-routing, and magnetics-layout guidance. The device is also limited to 10BASE-T operation, so it should not be treated as a drop-in solution for 100BASE-TX or gigabit Ethernet designs. This page combines the manufacturer’s product description, distributor package information, electrical limits, application guidance, and drop-in replacement analysis to help engineers evaluate the ENC28J60T-I/SO before schematic capture and PCB layout.

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ENC28J60T-I/SS

ENC28J60T-I/SS - 10BASE-T Ethernet Controller | Microchip

The Microchip Technology ENC28J60T-I/SS is a standalone 10BASE-T Ethernet controller with an integrated MAC and PHY, 8 KB of buffer RAM, and an SPI host interface in a 28-pin SSOP package. It operates from a 3.1 V to 3.6 V supply and supports SPI-based communication with a host microcontroller. The controller is designed to add wired Ethernet connectivity to embedded systems without requiring a separate MAC, physical-layer transceiver, or host-side Ethernet protocol stack. An Ethernet controller is an interface IC that manages the hardware-level transfer of frames between a host processor and a physical network. The ENC28J60 combines three principal functions in one device: a media access controller for Ethernet frame handling, a 10BASE-T PHY for connection to twisted-pair cabling, and a serial peripheral interface for communication with the host. This integration places the part within the broader hierarchy of network interface controller, interface IC, and semiconductor categories. Key features include support for IEEE 802.3 specifications, multiple packet-filtering schemes, an internal DMA module for fast data throughput, hardware-assisted checksum calculation, and an interrupt output for host notification. Its 8 KB buffer RAM allows Ethernet data to be buffered between network activity and host transactions. The 3.1 V to 3.6 V operating range and approximately 160 mA supply current are suitable for systems using a regulated 3.3 V rail. The ENC28J60 architecture separates host access from Ethernet processing through SPI while handling lower-level network tasks internally. Hardware-assisted checksums reduce processing load on the host microcontroller, while the internal DMA supports efficient movement of packet data. The manufacturer datasheet also notes that the oscillator requires a parallel-resonance crystal and provides examples for both crystal and external-clock arrangements, giving designers several implementation options for the timing subsystem. Typical applications include industrial Ethernet nodes, building-automation endpoints, embedded web servers, data loggers, access-control terminals, and IoT gateways that require a compact 10BASE-T network interface. It is especially useful where the host already has an SPI peripheral and board area is constrained. Because the controller supports only 10BASE-T, design engineers should evaluate it against current network requirements rather than assume support for 100BASE-TX or gigabit Ethernet. A key design consideration is the Ethernet physical-layer implementation. Follow the manufacturer’s recommended oscillator, magnetic-isolation, and termination circuits, and place the high-speed differential network section away from noisy digital and switching-power circuitry. Because the host must initialize the controller and interpret interrupts, firmware support for the ENC28J60 register and buffer model is also required. This product page combines the manufacturer’s core controller specifications with practical implementation guidance, qualified comparison points, and design notes that help engineers evaluate the ENC28J60T-I/SS before committing a compact embedded Ethernet design to production.

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ENC28J60T/ML

ENC28J60T/ML - 10Mbps SPI Ethernet Controller | Microchip

The Microchip Technology ENC28J60T/ML is a 28-pin, 10Mbps stand-alone Ethernet controller with an integrated MAC and 10BASE-T PHY, an 8 Kbyte packet buffer, and an SPI serial interface in a 28-VQFN exposed-pad package. It operates from a 3.1 V to 3.6 V supply and is designed to add Ethernet connectivity to microcontrollers, programmable controllers, and other embedded systems equipped with SPI. An Ethernet controller is an interface IC that manages the lower-level tasks required for a host processor to communicate over an Ethernet network. Within the product hierarchy, the ENC28J60 is a stand-alone Ethernet controller, a network interface controller with integrated media-access control and physical-layer functions. Its combination of an SPI host interface and integrated 10BASE-T PHY reduces the number of external network-interface components required by an embedded design. Key features include IEEE 802.3-compatible Ethernet operation, 10Mbps networking, an integrated MAC and 10BASE-T PHY, and 8 Kbytes of transmit and receive packet-buffer SRAM. The SPI interface allows register and buffer access from a host controller. The device is supplied in a compact 28-VQFN package with an exposed pad, making it suitable for space-constrained embedded equipment where soldered surface-mount construction is preferred. The ENC28J60 architecture places the Ethernet MAC and PHY inside one package while retaining packet storage on the controller. This allows a host microcontroller to exchange Ethernet frames through SPI without implementing the complete Ethernet physical and data-link layers itself. According to the Microchip ENC28J60 documentation, the controller meets the relevant IEEE 802.3 requirements for 10BASE-T operation and supports both transmission and reception through the integrated packet buffer. Typical applications include industrial monitoring equipment, building-automation endpoints, environmental sensors, connected control systems, and compact embedded gateways. The controller is particularly useful when the host processor needs only 10BASE-T connectivity and has limited I/O or processing capacity. SPI-based register access also makes the ENC28J60 practical for platforms where parallel host buses would consume too many pins. Designers should provide a compliant 3.3 V supply, adequate 10BASE-T magnetic-interface components, and layout that minimizes Ethernet signal integrity and EMI issues. The exposed thermal pad requires suitable PCB copper and thermal-via treatment. Firmware must also handle ENC28J60 initialization, interrupt servicing, descriptor management, and network-driver behavior rather than treating the controller as a protocol-independent plug-in peripheral. This page consolidates verified manufacturer and distributor information, package details, sourcing data, and replacement guidance. It also separates true same-footprint candidates from cross-package Ethernet alternatives so engineers can evaluate PCB compatibility before making a design change.

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ENC28J60T/SO

ENC28J60T/SO - 10BASE-T Ethernet Controller with SPI | Microchip

The Microchip ENC28J60T/SO is a 28-pin stand-alone Ethernet controller with an integrated 10BASE-T PHY and MAC, an SPI host interface, and 8 Kbytes of packet buffer RAM, powered from a 3.1 V to 3.6 V supply and offered in a 28-SOIC package. An Ethernet controller (also called a network interface controller or NIC) is a semiconductor that sits between a host microcontroller and the physical copper network. It performs the hardware-intensive layer-1 and layer-2 work — line coding, Manchester encoding, preamble generation, CRC generation and checking, frame filtering — so the host only has to move payload bytes over a simple serial bus. The ENC28J60T/SO belongs to the controller IC family, which is itself a subset of interface ICs within the broader semiconductor category. Key features include full IEEE 802.3 compliance for 10BASE-T half-duplex Ethernet, a full duplex-capable integrated MAC, a hardware-assisted checksum calculation engine for TCP, UDP, and IP headers, an internal DMA engine for high-throughput data movement, several programmable packet filtering schemes, and two dedicated LED outputs for link and network-activity indication. A non-blocking internal DMA engine means the host SPI bus is not stalled during frame processing. Technically, the device is a 3.3 V CMOS part with a maximum supply current of 160 mA, and its SPI CS, SCK, and SI inputs plus the RESET input are 5 V tolerant, allowing direct hookup to legacy 5 V host logic in many designs. An 8 Kbyte transmit/receive dual-port buffer SRAM holds packets in either direction, while the SPI interface runs up to 20 MHz-class host clocking and uses a simple four-wire serial protocol (SCK, SI, SO, CS) plus an interrupt output and a reset input. External magnetics — an Ethernet isolation transformer with integrated center-tap bias — and an RJ45 jack are required because the PHY itself is analog and transformer-based. Typical applications include low-cost embedded web servers, industrial sensor gateways, PLC and HMI retrofit modules, home-automation nodes, printers, and industrial data loggers that need TCP/IP connectivity without an external Ethernet bridge. The device is also a common choice in maker and education platforms because the SPI interface is simple and a complete TCP/IP stack is available in widely used open-source libraries. Design considerations center on the analog side of the board: keep the RBIAS network, 25 MHz crystal, 1.0 uF and 1.0 uF bias capacitors, and the PHY-to-transformer trace short and isolated from switching nodes, and provide a solid ground plane directly under the analog supply pins. On the digital side, add a level translator if the host runs at 5 V and drives the device's interrupt or receives its SPI output, because those outputs are 3.3 V CMOS levels. This page consolidates the manufacturer datasheet details, pin and package constraints, package-qualified drop-in alternatives, and practical layout and power notes for engineers who need a compact single-chip 10BASE-T network port rather than a modular SPI-to-Ethernet solution.

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ENC28J60T/SS

ENC28J60T/SS - 10Mbps SPI Ethernet Controller | Microchip

The Microchip Technology ENC28J60T/SS is a standalone 10BASE-T Ethernet controller with an integrated MAC and PHY, 8 KB of buffer RAM, and an SPI serial interface. It operates from a 3.1 V to 3.6 V supply and supports 10 Mbps Ethernet in a 28-pin SSOP package. By combining the Ethernet controller and physical-layer functions in one device, the ENC28J60T/SS provides a compact network interface for embedded systems. An Ethernet controller is an interface IC that connects a host processor to a physical Ethernet network. The ENC28J60 belongs to the broader Ethernet interface controller and network interface controller hierarchy, with the SPI interface acting as its connection to the embedded host. Its integrated MAC organizes frame transmission and reception, while the integrated 10BASE-T PHY handles the physical-layer signaling required by a 10BASE-T network. The primary feature set includes support for 10 Mbps operation, an 8 KB packet buffer, SPI host connectivity, and an integrated MAC and PHY. The 3.1 V to 3.6 V operating supply range places the device in a 3.3 V system environment, while the typical supply-current listing of 160 mA provides a useful baseline for power budgeting. The 28-SSOP package measures 5.30 mm wide by 0.209 inch, supporting compact embedded board layouts without requiring a large QFN footprint. The architecture makes the ENC28J60T/SS suitable for designs where an MCU or MPU lacks a native Ethernet MAC. The host communicates through the SPI interface, while the controller handles Ethernet framing, address filtering, buffering, and physical-layer communication. Packet filtering reduces the processing burden on the host by allowing selected traffic to be filtered within the controller, and the 8 KB buffer provides temporary storage for frames moving between the SPI host and Ethernet network. Typical uses include industrial automation controllers, embedded monitoring equipment, access-control terminals, building-network nodes, and IoT gateways with legacy 10BASE-T infrastructure. The part is most appropriate where 10 Mbps is sufficient and the PCB already includes a suitable Ethernet transformer, magnetics, connector, protection network, and controlled-impedance layout. Designers should allocate a 3.3 V supply with adequate transient margin and account for the listed 160 mA operating current when sizing regulators and copper. The SPI bus must meet the controller's timing requirements, while the Ethernet magnetics and copper path must be laid out according to the manufacturer datasheet. Firmware must also support the ENC28J60 register model, packet filtering, buffer management, and link-state behavior. This page combines verified manufacturer and distributor data with application guidance, comparison rows, design notes, and sourcing information. It distinguishes confirmed attributes from unavailable details so engineers can identify the documented 10 Mbps, 3.3 V, 8 KB, and 28-SSOP characteristics without relying on an unverified substitute specification.

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ENC424J600-I/ML

ENC424J600-I/ML 10/100 Ethernet Controller | Microchip

The Microchip Technology ENC424J600-I/ML is a stand-alone 10/100 Base-T Ethernet interface controller with an integrated MAC and PHY, an industry-standard SPI or parallel interface, and a 44-QFN package. It operates from a 3 V to 3.6 V supply, supports an operating temperature range of -45°C to +85°C, and is identified in the supplied data as a 10 Mbps Ethernet controller with 117 mA supply current. What is an Ethernet controller? An Ethernet controller is an interface IC that connects an embedded processor or microcontroller to an Ethernet physical network. This particular device combines a Media Access Control layer, or MAC, with a physical-layer transceiver, or PHY, allowing a host processor to exchange Ethernet traffic through SPI or a parallel host interface. It supports the IEEE 802.3 requirements applicable to 10Base-T and 100Base-TX Ethernet, including optional auto-negotiation behavior described by the manufacturer. The ENC424J600 family is intended to reduce the host-side implementation burden of a wired Ethernet connection. The manufacturer describes a low-cost stand-alone controller with packet filtering and a factory-programmed unique MAC address in product-page results. The supplied search data also identifies a 24-Kbyte on-chip RAM buffer for the family, while the ENC624J600 family shares the broader 10/100 Ethernet controller positioning. Exact feature availability for this orderable MPN should be confirmed in the manufacturer datasheet. The controller is relevant to embedded systems that need 10/100 Ethernet connectivity without implementing the physical network interface directly. Its SPI interface is useful for microcontrollers with limited parallel I/O, while the parallel interface can serve systems with an external bus. The -45°C to +85°C operating range covers industrial temperature requirements, subject to the complete electrical and qualification limits in the datasheet. Typical uses include industrial monitoring equipment, embedded control systems, data-acquisition units, factory interfaces, and network-connected embedded products. The Ethernet PHY requires appropriate magnetics, routing, termination, and layout implementation; the controller does not eliminate the need for a compliant external network interface. For a new design, verify the exact package dimensions, pin names, exposed-pad connection, clock requirements, host protocol, and recommended magnetic components in the Microchip datasheet. The 3 V supply range and -45°C to +85°C rating are useful starting constraints, but they should not replace review of absolute maximum ratings, timing, reset behavior, and Ethernet system requirements.

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ENC424J600-I/PT

ENC424J600-I/PT - 10/100 Ethernet Controller | Microchip

The Microchip Technology ENC424J600-I/PT is a stand-alone 10/100 Base-T Ethernet controller with an integrated MAC and PHY, a 3.3 V supply range, SPI and parallel host interfaces, and a 44-lead TQFP package measuring 10 x 10 mm. It supports 10 Mbps and 100 Mbps Ethernet operation according to the manufacturer datasheet. An Ethernet controller is a mixed-signal network interface IC that connects an embedded host to a physical Ethernet network. This device combines the media access controller, physical-layer transceiver, packet filtering, hardware cryptographic security engines, and a factory-programmed unique MAC address. That integration reduces the external component count compared with separate MAC and PHY designs. Key verified features include IEEE 802.3 support for 10Base-T and 100Base-TX, auto-negotiation, packet-filtering schemes, SPI or parallel interfacing, and a 24-Kbyte on-chip RAM buffer. The parallel option is especially useful for hosts that lack a sufficiently fast SPI interface or need deterministic register and packet-buffer access. The ENC424J600 family is architecturally positioned between simple SPI Ethernet modules and highly integrated host Ethernet interfaces. SPI reduces host pin count and simplifies connections to microcontrollers, whereas the parallel interface can offer greater throughput. Firmware must support the controller registers, buffer format, interrupt behavior, and Microchip network stack expectations. Typical uses include industrial control systems, embedded data acquisition units, building-automation controllers, serial-to-Ethernet gateways, test equipment, and compact embedded platforms. The integrated PHY removes the need for a separate Ethernet transceiver, while the on-chip packet buffer allows the host and Ethernet interface to operate more asynchronously. PCB implementation must follow the manufacturer’s pinout and layout guidance, particularly for the crystal or clock circuitry, decoupling, reset, and mixed-signal PHY connections. A 3.3 V system also needs to confirm that every connected host signal remains within the device’s verified electrical limits. This page consolidates manufacturer and distributor data with package, sourcing, interface, and replacement guidance that is not presented as one integrated engineering record elsewhere.

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ENC424J600T-I/ML

ENC424J600T-I/ML - 10/100 Ethernet Controller | Microchip

The Microchip Technology ENC424J600T-I/ML is a standalone 10/100 Base-T Ethernet controller with an integrated MAC and PHY, an industry-standard SPI interface, and a parallel interface option, supplied in a 44-lead QFN exposed-pad package. It operates from a 3.0 V to 3.6 V supply and is specified at 96 mA supply current. The device supports 10Base-T and 100Base-TX Ethernet in accordance with applicable IEEE 802.3 requirements. An Ethernet controller is an interface IC that connects a host processor to a physical Ethernet network. In the product hierarchy, this stand-alone controller integrates functions otherwise divided among a network interface controller, media-access control, and physical-layer transceiver. ENC424J600 is designed for embedded systems whose host MCU or processor lacks an economical Ethernet interface, allowing network connectivity to be added through SPI or a parallel host bus. Key features include an integrated 10/100 Base-T PHY, hardware cryptographic security engines, factory-programmed unique MAC addressing, packet-filtering functions, and support for auto-negotiation. The manufacturer documentation identifies a 24 Kbyte on-chip RAM buffer. These functions allow the controller to filter incoming traffic and support network management requirements while keeping host-side configuration relatively straightforward. The ENC424J600 architecture combines a high-speed receive-path ADC, DSP-based waveform decoding, MAC functions, and PHY circuitry in one package. IEEE 802.3-compatible Ethernet operation covers 10 Mbps and 100 Mbps links, while auto-negotiation allows the PHY to participate in selecting the common link rate with the connected network equipment. The 3.3 V supply range also aligns with many embedded processor platforms. Typical uses include industrial Ethernet gateways, embedded network appliances, programmable controllers, serial-to-Ethernet equipment, and compact monitoring systems. The controller is especially useful when a host processor already has SPI or parallel-interface resources and the board needs an autonomous 10/100 Ethernet endpoint rather than a high-speed multi-gigabit interface. PCB implementation requires careful high-speed layout around the PHY, magnetics, clocks, and supply rails. The exposed thermal pad should be connected to the ground plane with an appropriate thermal-via arrangement, and the Ethernet magnetics and transmission-line geometry should follow the manufacturer's reference layout. Verify regulatory Ethernet compliance in the final product because controller-level IEEE support does not replace system-level EMC testing. This product record combines the verified Microchip product information with distributor availability data, package details, and practical design guidance. It also distinguishes a genuine same-package replacement from related variants that require a different footprint, helping engineers compare procurement choices without assuming that a similar Ethernet controller is pin-compatible.

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ENC424J600T-I/PT

ENC424J600T-I/PT - 10/100 Ethernet Controller | Microchip

The Microchip Technology ENC424J600T-I/PT is a stand-alone 10/100 Base-T Ethernet controller with an integrated MAC and PHY, SPI and parallel interfaces, and a 44-TQFP package measuring 10 mm by 10 mm. It operates from a 3 V to 3.6 V supply and is identified in distributor data as an Ethernet controller for embedded systems. An Ethernet controller is a network interface semiconductor that manages frame transmission, reception, packet filtering, and the physical-layer electrical connection to 10/100 Base-T Ethernet. The ENC424J600 combines the MAC and PHY in one device, reducing external interface circuitry and allowing an embedded processor to connect through SPI or a parallel host interface. According to the Microchip ENC424J600/624J600 datasheet, the device meets applicable IEEE 802.3 requirements for 10Base-T and 100Base-TX Ethernet, including optional auto-negotiation functionality. The manufacturer description also identifies hardware cryptographic security engines, while the verified distributor listing identifies the target as a 10/100 Base-T controller with SPI and parallel interfaces. The part is supplied from a 3 V to 3.6 V operating range, with a distributor specification listing 96 mA supply current. Its 44-TQFP exposed-pad package is intended for surface-mount PCB assembly and provides a defined thermal and electrical land pattern for Ethernet interface designs. Typical application domains include embedded industrial controllers, networked instrumentation, data-acquisition equipment, access-control systems, and compact control platforms that require wired Ethernet without an external Ethernet PHY. The integrated MAC/PHY arrangement is useful where board space and interface simplicity matter, while the SPI option can reduce host pin requirements compared with a parallel bus. Designers should verify the exact pinout, exposed-pad connection, clock requirements, transceiver magnetics, RJ-45 integration, and decoupling requirements against the current Microchip datasheet before layout release. The verified data does not provide pricing, detailed timing values, temperature limits, or a complete pin map, so those items should not be inferred from generic Ethernet-controller specifications.

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EP1810GC-35

EP1810GC-35 - UV PLD, 40ns, CMOS, CPGA68 | Altera / Rochester

The Altera EP1810GC-35 is a high-performance Erasable Programmable Logic Device (EPLD) based on CMOS technology, packaged in a 68-pin Ceramic Pin Grid Array (CPGA68). It features up to 64 inputs and 48 outputs, with a propagation delay of 40 ns (the "-35" speed grade) and is supplied as a UV-erasable variant for prototyping and low-volume applications. The device is currently supported through Rochester Electronics, the authorized continuing-source partner for legacy Altera (now Intel FPGA) EPLD products. An EPLD (Erasable Programmable Logic Device) is a type of Programmable Logic Device (PLD) that uses UV-erasable EPROM cells to store the user's logic configuration. EPLDs sit in the broader taxonomy of programmable logic devices, between simple SPLDs/PLAs and more complex CPLDs/FPGAs. The EP1810GC-35 belongs to the Classic EPLD family, which targets glue-logic integration in systems where deterministic timing and short propagation delays matter more than raw logic density. CPLDs and FPGAs are now the mainstream alternatives, but classic UV EPLDs remain in service in long-lifecycle industrial, aerospace, and military programs. Key specifications include 16 macrocells (industry-standard terminology for this family), a maximum propagation delay of 40 ns, TTL-compatible I/O, and a maximum clock frequency determined by the tpd figure. The CPGA68 ceramic package is a through-hole Pin Grid Array rated for the extended industrial and military temperature range, which is the reason CPGA variants remain popular for high-reliability applications. The device is programmed via the Altera classic programming algorithm and erased by exposing the quartz window to UV light, allowing multiple reprogramming cycles during development. Typical applications include bus-interface glue logic, address decoding, state-machine implementation, and interrupt prioritisation in legacy industrial controllers, avionics subsystems, and military-grade embedded systems. The deterministic 40 ns delay and TTL I/O make it straightforward to use as a drop-in replacement for discrete 74-series glue logic, while consolidating dozens of packages into a single programmable device. Designers should verify the supply voltage and I/O standard against the original system specification before substituting a CPLD, since newer CMOS-only families require different programming voltages. For long-life-cycle programs, sourcing the EP1810GC-35 through Rochester Electronics ensures continued support and traceability under the original Altera datasheet specification. This page consolidates verified distributor pricing, pin-compatible alternatives, and design notes not found on a single OEM page.

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EP1810GC-35AB

EP1810GC-35AB - Classic EPLD, 48 Macrocells, 35ns | Altera

The Altera EP1810GC-35AB is a member of the Classic EPLD family, a high-performance CMOS Erasable Programmable Logic Device offering up to 64 inputs, 48 outputs, and 48 macrocells in a Pin Grid Array (PGA) package. Built on advanced CMOS EPROM technology, this part delivers high-speed, low-power logic integration with a maximum propagation delay of 35 ns and is offered in a ceramic PGA package with the speed grade suffix "-35". What is an EPLD? An EPLD (Erasable Programmable Logic Device) is a type of programmable logic device that uses EPROM or EEPROM cells to store the configuration, allowing the device to be erased with ultraviolet light and reprogrammed. EPLDs sit in the broader programmable logic hierarchy: programmable logic -> EPLD -> CPLD -> programmable logic IC -> semiconductor. They offer predictable timing, deterministic pin-to-pin delays, and are typically used as "glue logic" to replace multiple discrete SSI/MSI logic gates, providing design flexibility without the complexity of an FPGA. Key features of the EP1810GC-35AB include 48 macrocells, 12 dedicated input pins, 48 I/O pins, a maximum propagation delay (tPD) of 35 ns, and a maximum toggle frequency of 62.5 MHz. The device is fabricated on a low-power CMOS EPROM process, supports in-system programmability via a JTAG-like interface, and retains its configuration for at least 10 years. The ceramic PGA package provides robust thermal performance suitable for industrial and military temperature grades. From an architectural standpoint, the EP1810GC-35AB uses a sum-of-products architecture with a programmable AND/OR array feeding output macrocells. Each macrocell contains a flip-flop and programmable I/O controls for registered, combinational, or bidirectional operation. The device includes a global clock network, asynchronous clear, and output enable controls, enabling the implementation of complex state machines and interface logic. Typical applications include high-speed bus decoding, address mapping in 8-bit and 16-bit microprocessor systems, state-machine implementation, glue-logic replacement for multiple 74LS/74F-series TTL gates, and industrial control systems. The Classic EPLD family is also widely used in legacy telecom infrastructure, military/aerospace systems, and test equipment where long-term lifecycle support and known-good silicon are essential. When designing with the EP1810GC-35AB, note that this device is part of an obsolete product line; engineers should verify long-term availability with authorized distributors or consider modern Altera/Intel MAX series CPLDs as a redesign path. The ceramic PGA package requires a socket or careful PCB layout for the through-hole pin array.

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EP1810GI-45

EP1810GI-45 - UV PLD, 50ns, 24 Macrocells, CPGA-68 | Altera

The Altera EP1810GI-45 is a UV-erasable programmable logic device (PLD) from the Altera Classic EPLD family, housed in a 68-pin Ceramic Pin Grid Array (CPGA-68) package with an integrated quartz window for in-system erasure. It provides 24 macrocells, 48 flip-flops, and a propagation delay of 45 ns (the -45 speed grade) over the commercial operating range, with a maximum toggle frequency rated in the EPLD Classic family for combinational and registered logic implementation. A UV-erasable PLD (also called an EPLD or erasable programmable logic device) is a non-volatile logic IC that can be configured by the user to implement custom combinational and sequential logic. PLDs sit within the broader programmable logic hierarchy that includes PROMs, PALs, GALs, CPLDs, and FPGAs; the Classic EPLD family represents one of the earliest erasable, macrocell-based PLD architectures. Programming is performed electrically via a dedicated programmer, and erasure is achieved by exposing the die through the quartz window to ultraviolet light, after which the device can be reprogrammed - making EP1810GI-45 well suited to prototype and low-volume production environments. Key features include 24 dedicated macrocells, 48 flip-flops, 45 ns propagation delay (tpd), and CMOS technology for low power operation. The CPGA-68 ceramic package with UV window supports field reprogramming, while the 45 ns speed grade enables use in glue-logic, bus interfacing, state-machine control, and address decoding roles in legacy systems. The device is offered in -45 (45 ns) and -35 (35 ns) speed grades within the same Classic EPLD architecture. In a typical application, the EP1810GI-45 implements glue logic between microprocessors and peripherals, replacing multiple discrete 74-series logic ICs with a single programmable device. The CMOS process keeps quiescent power low, while the ceramic PGA package and integrated UV window make it straightforward to erase and reprogram during development. The 45 ns propagation delay is sufficient for asynchronous bus decoding, register-decode multiplexing, and glue logic in systems running at MHz-class clock rates. Typical applications include legacy industrial control logic, replacement of discontinued 74-series discrete logic, address decoding, state-machine controllers, I/O expansion for older microprocessors, and military/aerospace systems where the ceramic package and known Altera Classic EPLD silicon are required. The UV-erasable window also makes it suitable for secure prototyping where bitstream erasure between builds is mandatory. When designing with EP1810GI-45, ensure the programmer socket supports the 68-pin CPGA pinout and the device is erased with the correct UV dose prior to reprogramming. The ceramic CPGA package is through-hole and not RoHS-equivalent; for new designs consider modern surface-mount CPLDs in QFP or BGA packages with similar macrocell counts. Stock is supported by Rochester Electronics as an authorized Altera Classic EPLD franchise partner.

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EP1810GM/883B

EP1810GM/883B - Classic EPLD 100MHz PGA-181 | Intel / Altera

The Intel (formerly Altera) EP1810GM/883B is a member of the Altera Classic EPLD family, providing high-speed, low-power CMOS programmable logic in a military-grade ceramic Pin Grid Array package (PGA-181). The device delivers pin-to-pin logic delays as low as 10 ns and counter frequencies up to 100 MHz, making it one of the fastest eras of classic-era programmable logic for glue-logic and decoder applications. The /883B suffix indicates MIL-STD-883 Class B screening for aerospace, defense, and high-reliability industrial systems. An EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC that preceded modern CPLDs and FPGAs. EPLDs use EPROM/EEPROM cells to define AND/OR macrocell logic that implements Boolean sum-of-products expressions. They occupy the middle ground between PALs (too few gates) and FPGAs (more flexible but slower and more power-hungry in this era), offering deterministic 10 ns tPD with predictable timing — ideal for address decoding, bus interface logic, and state-machine replacement in legacy systems. Key features of the EP1810GM/883B include approximately 900 usable gates, 48 macrocells, and 6 dedicated input pins plus 48 I/O pins routed through the classic interconnect. The 181-pin PGA package supports high signal integrity for the 48 bidirectional I/Os and is screened to MIL-STD-883 Class B for operation across the military -55C to +125C temperature range. The 0.8 micron CMOS EPROM process yields low standby current and 5V-tolerant inputs on a single 5V supply. Architecturally, the EP1810 uses a programmable AND array feeding fixed OR terms within each macrocell, with each macrocell offering a flip-flop for registered outputs. The classic interconnect delivers 10 ns pin-to-pin with no skew variation across the die, which is a key differentiator versus early FPGAs. The device is in-system programmable via a JTAG-like serial interface (compatible with Altera's MAX+plus II legacy flow) and supports 100% AC testing per MIL-STD-883. Typical applications include military avionics bus interfaces (MIL-STD-1553 glue logic), legacy radar system timing, industrial CNC controller decode logic, replacement of multiple TTL/CMOS PALs in defense electronics, and high-reliability address decoding for VME and VXI backplanes. The ceramic PGA package is preferred in environments with hermetic-seal requirements. When designing with this part, ensure your programmer supports the Altera Classic device family (MAX+plus II or a compatible vintage toolchain). The 181-pin PGA footprint requires a socketed through-hole PCB layout, and obsolete-toolchain support must be maintained across the product lifecycle.

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EP1810GM883

EP1810GM883 - 48-Macrocell Classic EPLD, 5V, 68-Pin PGA | Altera

The Altera EP1810GM883 is a UV-erasable programmable logic device (EPLD) from the Altera Classic EPLD family, integrating 48 macrocells, 48 I/O pins, and 12 dedicated inputs on a single CMOS die in a 68-pin ceramic Pin Grid Array (PGA) package. It targets high-speed, low-power logic integration with a maximum toggle frequency of 80 MHz and a pin-to-pin propagation delay of 45 ns, supplied from a single 5 V rail (4.5 V to 5.5 V). The device is built on advanced CMOS technology, packaged in a ceramic metal-sealed cofired enclosure, and qualified to MIL-STD-883 Class B (the '883' suffix denotes 883B processing), making it suitable for military and aerospace programs that require hermetic, screened parts. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic IC that combines the flexibility of a PLD with EPROM-based configuration memory. In the broader taxonomy, EPLDs sit between simple PALs and large FPGAs: they offer deterministic timing, low power, and instant-on behavior because the configuration is stored in on-chip UV-erasable cells rather than loaded from external flash at boot. The Classic EPLD family was Altera's flagship high-speed programmable logic line in the late 1980s and 1990s, before being superseded by MAX-series CPLDs and modern SRAM-based FPGAs. Key features include 48 macrocells interconnected by global and local buses, four global clock inputs, a synchronous or asynchronous clear per macrocell, programmable output slew rate, and 48 bidirectional I/O lines that can be individually configured as input, output, or bidirectional. The shared-logic architecture lets designers build state machines, address decoders, glue logic, and bus arbiters in a single device that replaces dozens of SSI/MSI 74-series parts, while the ceramic PGA package gives excellent thermal performance and reliable operation across the full military temperature range. Typical applications include MIL-STD-1553 interface glue logic in avionics, radar signal-conditioning front ends, missile guidance subsystems, satellite payload control boards, and other mission-critical defense platforms where hermetic packaging and 883B screening are mandated. Industrial high-reliability systems (down-hole oil and gas, nuclear instrumentation) also benefit from the wide operating margin and deterministic timing. When designing with this device, ensure the board supplies a clean 5 V rail with decoupling within 1 cm of every supply pin, and reserve a windowed ceramic adapter for UV erasure during prototyping. The part is pin-compatible with the full EP1810 family, so designers can substitute speed grades (35 ns, 45 ns, 55 ns) and package variants (PGA, PLCC, ceramic and plastic) without PCB rework. For modern production builds, designers should evaluate MAX7000AE or MAX V CPLDs as functional refreshes, although the pinout is not drop-in compatible with the EP1810. This page synthesizes distributor inventory, mil-spec screening details, and cross-family drop-in alternatives that are not consolidated on any single distributor or manufacturer page, including the EP1810 family members and contemporary Classic EPLD speed grades that share the same 68-pin PGA footprint.

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EP1810GM883B

EP1810GM883B - 48-Macrocell EPLD, 5V CMOS, 883B Military | Altera

The Altera EP1810GM883B is a UV-erasable, high-performance CMOS Erasable Programmable Logic Device (EPLD) from the EP1810 family, supplied in a ceramic 84-pin Grid Array package (suffix GM) processed to MIL-STD-883B (Class B) screening. The device integrates 48 macrocells, 60 inputs (12 dedicated, 48 I/O), and offers up to 64 user-configurable flip-flops for glue-logic and state-machine integration in military and aerospace designs. The '883B' suffix denotes 883B processing, which adds extended temperature operation and burn-in screening for high-reliability applications. An EPLD (Erasable Programmable Logic Device) is a non-volatile, reprogrammable logic IC that combines AND/OR array architecture with output macrocells, allowing designers to implement custom combinational and sequential logic without discrete TTL/CMOS gates. EPLDs sit in the programmable logic hierarchy between simple PAL/GAL devices and larger CPLDs/FPGAs, offering fast pin-to-pin propagation delays (around 15-50 ns), predictable timing, and one-time or UV-reprogrammable development cycles. They are widely used as address decoders, bus interfaces, state machines, and peripheral glue logic in long-lifecycle industrial, telecom, and defense systems where ASIC redesigns are impractical. Key features of the EP1810GM883B include a 50 ns maximum propagation delay (tPD), 4.5 V to 5.5 V single-supply CMOS operation, 100 MHz maximum toggle frequency on internal flip-flops, and 48 macrocells each with programmable I/O polarity and feedback. The CMOS process yields low standby current and TTL-compatible I/O levels, while the 883B processing ensures operation across the -55 °C to +125 °C military temperature range with screened reliability. Architecturally, the EP1810 family uses Altera's classic MAX-style macrocell structure with a programmable AND array feeding a fixed OR array, plus per-macrocell flip-flops with programmable clock, clear, and preset. The 48 I/O pins are bidirectional with tri-state control, and the 12 dedicated inputs feed the array without consuming macrocell resources. JTAG-like or Altera-specific programming (via MasterBlaster/ByteBlaster on production parts) is supported, and the ceramic PGA package supports hermetic military assembly. Typical applications include military/aerospace avionics, missile guidance electronics, ruggedized industrial controllers, legacy telecom infrastructure, and any long-lifecycle design where commercial-grade EPLDs have been qualified out but the original Altera pinout must be retained for form-fit-function drop-in replacement. Design considerations: the EP1810GM883B is a legacy 5 V part with TTL-compatible thresholds; input signals must remain within 0 V to VCC (5 V typical) and unused inputs must be tied to VCC or GND per Altera's Classic EPLD handbook to avoid noise-induced supply current. Designers migrating to modern 3.3 V systems should level-shift or select a newer MAX II/MAX V equivalent, but note that package and pinout changes may be required. This page synthesizes distributor pricing, same-family drop-in alternatives, and practical design notes not consolidated in the original Altera datasheet - useful for sustainment engineers managing long-lifecycle military programs.

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EP1810JC-25

EP1810JC-25 - 48-Macrocell Classic EPLD, 25ns tPD | Intel

The Intel (formerly Altera) EP1810JC-25 is a 48-macrocell Classic EPLD from the EP1810 family of high-performance CMOS Erasable Programmable Logic Devices, housed in a 28-pin ceramic DIP (J-package) windowed package with a 25 ns propagation delay grade. It integrates 60 input lines, 48 I/O lines, 12 dedicated inputs, and 4 dedicated clock inputs onto a single UV-erasable CMOS die, delivering glue-logic integration that historically replaced dozens of 74-series SSI/MSI parts on legacy 5 V designs. A Classic EPLD (Erasable Programmable Logic Device) is a member of the programmable logic family that sits between simple PAL/GAL devices and modern CPLDs/FPGAs in the design hierarchy. Like all EPLDs, the EP1810JC-25 is non-volatile (in its windowed ceramic form, erasable with UV light), deterministic in timing (fixed pin-to-pin delays), and ideal for decoder, bus-interface, and state-machine glue logic. The Classic EPLD family was Altera's first-generation architecture, predating MAX 7000 and MAX II series. Key specifications include 48 macrocells of AND/OR logic, a worst-case propagation delay (tPD) of 25 ns, and a maximum toggle frequency of roughly 50 MHz. The device operates from a single 4.75 V to 5.25 V supply and is offered in industrial temperature grades suitable for -40 °C to 85 °C operation. The ceramic windowed DIP package allows designers to erase and re-program the device under a UV eraser, making the -25 speed grade useful for prototyping and low-volume production. The architecture is a sum-of-products PLA-style fabric with each macrocell containing a programmable AND array feeding a fixed OR term, an output flip-flop, and a tri-state output buffer. Configurable output enables and feedback paths allow each macrocell pin to be used as input, output, or bidirectional I/O. Four dedicated global clock pins synchronize internal registers, eliminating skew issues common to discrete flip-flop designs. Typical applications include address decoding for 8086/Motorola 68000 microprocessor systems, bus arbitration, peripheral interface glue logic, industrial control state machines, and legacy telecom backplane controllers. Designers also use the EP1810JC-25 for hardware emulation of standard logic functions in board bring-up and for replacing obsolete 24-pin/28-pin PAL devices with greater logic density. When designing with this EPLD, remember that the ceramic DIP -25 speed grade is the slowest in the EP1810 family and is most often used for prototyping rather than production volume. Modern designs requiring the same logic should evaluate MAX 7000AE or MAX II CPLDs as functional successors, since the Classic EPLD family has been NRND for many years. This page synthesizes distributor pricing, drop-in compatible alternatives across speed grades, and practical design notes not found in the original Altera datasheet, providing information-gain content beyond what manufacturer or distributor pages typically offer.

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EP1810JC-35

EP1810JC-35 - 48-Macrocell UV EPLD, 35ns, CQCC-68 | Intel / Altera

The Intel / Altera EP1810JC-35 is a UV-erasable Complex Programmable Logic Device (CPLD) from the Classic EPLD family, featuring 48 macrocells with a maximum propagation delay of 35 ns and an internal interconnect fabric based on global and local buses. The device is housed in a 68-pin ceramic J-lead chip carrier (CQCC-68 / QCCJ) package suitable for commercial-temperature, through-hole-soldered legacy designs. According to manufacturer and distributor listings, the EP1810JC-35 is a CMOS, 5 V, non-volatile (UV-erase) programmable logic device intended for glue-logic and bus-interface replacement in industrial control, telecommunications, and military-aerospace ground-support equipment. What is a UV EPLD? An EPLD (Erasable Programmable Logic Device) is a class of programmable logic that combines AND/OR array structures with programmable macrocells and a programmable interconnect network. The UV-erasable variant (UVPLD) is programmed electrically and erased by exposing the die to ultraviolet light through a quartz window, allowing multiple design cycles during prototyping and field service. UV EPLDs sit between simple PAL/GAL devices and modern flash-based CPLDs in the programmable logic hierarchy, and they have been widely used in telecom, industrial, and defense systems since the mid-1980s because they provide deterministic propagation delay, non-volatile configuration, and superior pin-locking for through-hole PCB designs. Key features of the EP1810JC-35 include 48 macrocells, 35 ns worst-case pin-to-pin propagation delay (tpd), a maximum toggle frequency in the tens of megahertz range, and 68 J-lead ceramic interconnect pins rated for commercial-grade 0°C to 70°C operation. The device is fabricated in CMOS technology for low power consumption, supports 5 V standard logic interfaces, and provides a programmable output macrocell with configurable register/bypass, feedback, and tri-state options that simplify bus-interface, address-decoding, and state-machine integration. The EP1810JC-35 implements a classic sum-of-products logic architecture with each macrocell fed by a programmable AND array and feeding a programmable OR/registered output stage. This deterministic architecture, combined with non-volatile UV-erasable configuration memory, makes the part attractive for designs that require predictable timing analysis without needing the configuration controller or boot PROM required by SRAM-based FPGAs. The device is one of the slowest members of the EP1810 family and is typically selected where 35 ns timing comfortably meets the system clock period rather than requiring the 25 ns or 20 ns -25/-20 speed grades. Typical applications include glue-logic replacement for 74LS/74AS TTL in legacy telecom backplanes, address decoding and wait-state generation in 8086/80286 microprocessor systems, bus arbitration and interrupt controllers in industrial control cards, and avionics ground-test fixtures where non-volatile, deterministic logic is required and field-reprogrammability via UV erasure is acceptable. The 68-pin ceramic J-leaded package also supports MIL-STD-883B screening variants of the same die (EP1810GM/883B family) for harsher environments. When designing with the EP1810JC-35, verify timing against the 35 ns propagation delay budget, ensure programming is performed with a verified EP1810 device programmer (modern third-party programmers still support this legacy family), and consider migrating to a pin-compatible flash-based MAX 7000-series CPLD (such as EPM7128S in the same PLCC-84 / CQCC-68 footprint) for new designs where in-system reprogrammability is desired. Always use a quartz-windowed ceramic package if UV erasure is needed; otherwise, specify the OTP one-time-programmable variant for production boards. This page synthesizes distributor inventory, parametric data, and practical migration guidance not always found in the original Altera datasheet, helping engineers evaluate legacy EPLD options for both sustaining-engineering and modernization projects.

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EP1810JC-45

EP1810JC-45 - Classic EPLD, 48 Macrocells, 45ns, UV PLCC | Altera

The Intel / Altera EP1810JC-45 is a 48-macrocell Classic EPLD from Altera's EP1810 family, packaged in a 68-lead ceramic J-lead chip carrier (QCCJ / PLCC-68) and specified with a 45 ns maximum propagation delay. It is a UV-erasable, user-configurable LSI circuit capable of implementing approximately 2100 equivalent gates of conventional or custom logic, organized around a Programmable Logic Array with global and local interconnect buses. The '-45' speed suffix denotes a 45 ns tpd at commercial temperature grade, while the 'JC' suffix denotes the windowed ceramic J-lead chip-carrier package intended for prototyping and UV-erase cycles. A Classic EPLD (Erasable Programmable Logic Device) is a one-time- or UV-erasable non-volatile logic device that predates modern SRAM-based FPGAs and flash-based CPLDs. In the system hierarchy it sits between discrete 74-series glue logic and modern FPGA/CPLD architectures: each macrocell contains a programmable AND/OR array plus a flip-flop, and the global/local buses fan logic between the AND array and the macrocell register bank. Because the device is non-volatile and instantly reconfigurable without external boot memory, Classic EPLDs were widely used for address decoding, bus arbitration, state-machine control, and glue logic in 1980s and 1990s designs. Key features of the EP1810JC-45 include 48 macrocells, 12 dedicated inputs plus 48 bidirectional I/O lines for 60 total usable I/Os, a 33.3 MHz maximum clock frequency, and a 5.25 V maximum supply voltage with CMOS technology. The part is offered in a commercial temperature grade (typically 0C to 70C) and supports both synchronous and asynchronous logic designs via per-macrocell flip-flops with individual clear, preset, and output-enable control. Programming is performed via a standard Altera programming algorithm through the dedicated programming pins. Typical applications for the EP1810JC-45 include microprocessor address decoding, DMA control logic, peripheral-chip glue logic in 8-bit and 16-bit systems, bus-interface adapters, and replacement of multiple 74LS/74ALS TTL packages. The 2100-gate capacity also makes it usable for small state machines, interrupt controllers, and timing/sequencer functions in legacy industrial controllers and test equipment. When designing with this device, ensure that the supply voltage does not exceed 5.25 V and that high-speed signals use the dedicated fast-input pins rather than I/O pins. The windowed ceramic package allows repeated UV erasure, which is essential for prototype iteration - plan for a 30-60 minute UV erase cycle when iterating logic designs. The part is now in NRND/last-time-buy status at Altera/Intel, so long-term designs should consider modern MAX series replacements. This page synthesizes distributor pricing, package-level compatibility notes, and drop-in alternatives that are not consolidated in any single manufacturer document.

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EP1810JC35

EP1810JC35 - 48 Macrocell Classic EPLD 35ns CMOS PLCC-68 | Altera

The Altera EP1810JC35 is a 48-macrocell Classic-series Erasable Programmable Logic Device (EPLD) fabricated on a sub-micron CMOS process, packaged in a 68-pin J-lead ceramic chip carrier (PLCC-68) and specified at a 35 ns pin-to-pin propagation delay. It belongs to the Altera Classic EPLD family, a UV-erasable/OTP complex PLD line designed for high-speed, low-power logic integration in glue-logic, decoder, encoder, state-machine and bus-interface roles. The EP1810JC35 integrates 48 macrocells with 36 available I/O pins (the J-lead PLCC-68 variant), giving designers roughly 300 usable logic gates in a single device. A Complex Programmable Logic Device (CPLD / EPLD) is a non-volatile, instant-on programmable logic device that sits hierarchically between discrete 74-series glue logic and larger FPGA fabrics. It combines an AND/OR programmable array with registered or combinational macrocell outputs, retaining its configuration without external boot memory. Classic EPLDs such as the EP1810JC35 are widely used for deterministic, single-clock-cycle logic replacement where FPGAs would be over-sized or over-priced and where PAL/GAL devices lack the macrocell count. As a logic integration category, EPLDs belong to programmable logic devices, then programmable logic, then digital semiconductors. Key features of the EP1810JC35 include a 35 ns tPD (pin-to-pin delay), 5.25 V maximum VCC, commercial 0 C to +70 C operating range, ceramic J-lead PLCC-68 package with windowed UV-erasable die, and JTAG-/programmer-based configuration via Altera's MAX+plus II or A+plus development flow. The 48 macrocells are organized into four Logic Array Blocks (LABs) sharing a programmable interconnect array (PIA), giving the part deterministic, predictable timing. Compared to GAL/PAL devices, the EP1810 delivers higher macrocell density, multiple dedicated clock inputs, and architectural support for both D/T/JK flip-flop macrocell modes. Architecturally, the EP1810JC35 uses a CMOS EPROM-cell-based AND array driving a fixed OR array, with each macrocell offering configurable register polarity, output enable, and feedback. The 35 ns speed grade is one of three commonly offered grades (-25, -35, -45 ns) within the same PLCC-68 pinout, allowing designers to trade timing margin against cost without changing board layout. The J-lead ceramic package supports both windowed (erasable) and OTP usage; the 'C' suffix denotes commercial temperature grade. Typical applications include peripheral and memory-interface glue logic in legacy computing platforms, address decoding and wait-state generation in 80C186/80386-based embedded designs, bus arbitrators and interrupt controllers, high-speed state machines, and channelized industrial control logic. The 5 V tolerance and CMOS input structure make it well-suited to TTL-compatible buses that have since migrated to 3.3 V microcontrollers via simple level shifters. Programmable logic devices such as the EP1810JC35 are still supported for long-lifecycle defense and aerospace programs that value the part's ceramic packaging and proven reliability. When designing with the EP1810JC35, observe the 5.25 V absolute maximum VCC (use a regulated 5 V rail), provide proper decoupling (one 0.1 uF per VCC pin plus a bulk 10 uF), and route the dedicated clock and clear pins with controlled-impedance traces. Because the device is OTP/UV-erasable depending on lid variant, design engineers should plan for one-time programming orceramic-windowed erasure cycles during prototyping. This page synthesizes distributor pricing, drop-in alternatives, application examples and practical design notes not collated in the manufacturer datasheet, helping engineers source or substitute the EP1810JC35 for new designs or legacy repairs.

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EP1810JI-35

EP1810JI-35 - 48-Macrocell Classic EPLD, 35ns | Intel / Altera

The Altera EP1810JI-35 is a high-performance 48-macrocell Classic EPLD (Erasable Programmable Logic Device) fabricated on advanced CMOS technology, delivering high-speed, low-power logic integration in a 28-pin ceramic J-leaded (JLCC/CDIP) windowed package. According to the Altera EP1810 datasheet family, this device offers 35 ns pin-to-pin propagation delay (tPD) and operates as a pin-compatible member of the classic MAX-family EPLD architecture. The 'J' suffix indicates a ceramic windowed package suitable for prototyping and reprogramming, while the 'I' denotes the industrial temperature grade and the '35' marks the speed grade. A Classic EPLD is a non-volatile, reprogrammable logic device from the family that preceded modern CPLDs. Architecturally, it sits between discrete TTL glue logic and modern FPGAs: the EP1810 provides 48 macrocells organized as eight Logic Array Blocks (LABs) of 16 macrocells each, with 48 dedicated input pins and deterministic 35 ns combinational delay. This category of device was used for address decoding, bus interfacing, state-machine control, and peripheral glue logic before modern microcontrollers and small FPGAs absorbed most of those functions. Key features of the EP1810JI-35 include 48 macrocells, 48 dedicated inputs, programmable I/O architecture, JTAG-compatible in-system programmability on later variants, and power-down support. It is built on a UV-erasable CMOS EPROM cell, allowing laboratory reprogramming through the ceramic window. The industrial-grade temperature range (-40C to +85C) and 35 ns propagation delay make it suitable for legacy bus-interface designs where a true drop-in replacement is required for an end-of-life board. Typical applications include address decoding for microprocessor busses, state-machine and sequencer replacement of TTL/74LS glue logic, peripheral controllers in ISA/VME bus architectures, and prototyping platforms for industrial control systems. Engineers frequently select the EP1810JI-35 when maintaining long-lifecycle industrial equipment, defense/aerospace platforms, or test systems that were designed around this EPLD. When designing with this device, remember that the ceramic J-leaded (JLCC) package requires a through-hole footprint and cannot be substituted directly with surface-mount CPLD parts. Program the part with industry-standard EPLD programmers (e.g., Data I/O, BP Microsystems) using JEDEC fuse files generated from the Altera MAX+PLUS II legacy toolchain. This page synthesizes distributor stock and pricing for the EP1810JI-35, drop-in replacement analysis, and practical design notes not found in the legacy datasheet summary, so engineers can quickly evaluate lifecycle alternatives.

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EP1810JI-45

EP1810JI-45 - 48-Macrocell UV PLD, 33.3 MHz, 68-pin JLCC | Altera

The Altera EP1810JI-45 is a 48-macrocell CMOS Erasable Programmable Logic Device (EPLD) from the Classic EPLD family, housed in a 68-pin J-leaded ceramic chip carrier (JLCC, package code QCCJ) with industrial temperature grading. It delivers up to 33.3 MHz maximum operating frequency and 50 ns pin-to-pin propagation delay, supported by 48 configurable I/O lines and 12 dedicated inputs. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic IC that uses EPROM/EEPROM cells to retain its logic configuration. EPLDs belong to the broader PLD family (programmable logic device), which sits alongside FPGAs, CPLDs, and SPLDs in the programmable logic hierarchy. Unlike SRAM-based FPGAs, EPLDs retain their bitstream without external memory, simplifying board design and providing instant-on behavior. Key features of the EP1810JI-45 include 48 macrocells for combinational and registered logic, 33.3 MHz fMAX, 50 ns tPD, J-bend surface-mount terminals, and an industrial temperature range of -40 °C to +85 °C. The architecture integrates a programmable AND/OR array with feedback paths, enabling efficient implementation of state machines, decoders, and glue logic. The EP1810 series uses Altera's Classic EPLD architecture, which combines high-density macrocells with predictable timing that is independent of routing density. Each macrocell contains a programmable flip-flop and configurable output polarity, and the device is programmed via the Altera Master Programming Unit or compatible third-party programmers using the JEDEC fuse-map format. Typical applications include industrial control glue logic, address decoding in 8086/68000 microprocessor systems, bus interface adapters, state-machine controllers, and legacy replacement of discrete 74LS TTL logic. The wide 5 V supply tolerance and TTL-compatible I/O simplify integration into existing 5 V designs that require deterministic timing. When designing with the EP1810JI-45, note that it is a UV-erasable/OTP device - in-window ceramic parts require a UV eraser for reprogramming. Designers should also confirm programming algorithm support with current Altera (now Intel FPGA) tools, as the Classic EPLD family predates modern Quartus support. For new designs, the MAX series CPLDs are recommended successors. This page synthesizes distributor pricing, same-family drop-in alternatives, and pinout notes not found in the manufacturer datasheet - designed to help engineers source, replace, and qualify the EP1810JI-45 for both production and legacy maintenance.

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EP1810JM-45

EP1810JM-45 - 48 Macrocell Classic EPLD, 45ns, CMOS | Altera

The Altera EP1810JM-45 is a 48-macrocell Classic EPLD (Erasable Programmable Logic Device) from the EP1810 series, fabricated on advanced CMOS technology for high-speed, low-power logic integration. It features a 45ns maximum propagation delay (tpd) with the -45 speed grade suffix, operates from a single 4.5V to 5.5V supply, and is offered in a ceramic J-leaded chip carrier (JLCC-68, JM suffix) rated for the full military temperature range of -55C to +125C. The device contains 48 macrocells, each combining a programmable AND/OR array with a configurable flip-flop, providing roughly 900 usable gates of random logic integration in a single package. A Classic EPLD is a member of the Programmable Logic Device (PLD) family, sitting below CPLDs and FPGAs in the programmable logic hierarchy. Unlike SRAM-based FPGAs, the EP1810 uses non-volatile UV-erasable EPROM cells to store the logic configuration, giving it instant-on behavior at power-up with no external boot PROM required. This makes the EP1810JM-45 well suited to deterministic, low-latency glue-logic, decoder, and state-machine functions where an FPGA's boot time and complexity would be over-engineered. Key features include 45ns pin-to-pin propagation delay, 48 macrocells with user-programmable I/O polarity, 68 pins in a ceramic JLCC package, and CMOS-TTL compatible I/O. The J-grade package and military temperature rating place this part firmly in the legacy/mil-spec category for avionics, military communications, and long-lifecycle industrial equipment where Altera Classic EPLDs have decades of proven field reliability. Architecturally, the EP1810 implements a sum-of-products PLA structure with a global interconnect, replacing 5 to 15 SSI/MSI logic packages with one device. It is programmed via an industry-standard JEDEC fuse map using a conventional EPROM programmer; the windowed ceramic package allows erasure under UV light for prototyping and rework. Designers still maintain legacy EP1810 designs because the part is specified across the full military temperature range and has been second-sourced historically. Typical applications include military and avionics glue logic, industrial control state machines, address decoding for legacy microprocessors, and pin-compatible replacements for TTL 74LS/74F logic arrays. The instant-on UV-EPROM configuration eliminates the FPGA bitstream security and boot-time concerns that disqualify SRAM FPGAs in those environments. When designing with the EP1810JM-45, verify that the timing budget (45ns tpd worst-case plus setup/hold) fits the system clock. Program the device using a JEDEC file generated by Altera MAX+PLUS II or a compatible legacy toolchain, and ensure the ceramic windowed package receives a proper IC socket or socketed footprint for UV erasure during prototyping. This page synthesizes distributor pricing, same-package drop-in alternatives from the EP1810 family, and practical design notes not found in the original Altera datasheet. All specifications below are derived from the Altera EP1810 Classic EPLD datasheet (Classic EPLD Family, 41 pages) and current distributor listings as of 2026-09-06.

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ENC28J60T-I/ML - 10BASE-T Ethernet Controller | Microchip

ENC28J60T-I/SO 10BASE-T Ethernet Controller | Microchip Technology

ENC28J60T-I/SS - 10BASE-T Ethernet Controller | Microchip

ENC28J60T/ML - 10Mbps SPI Ethernet Controller | Microchip

ENC28J60T/SO - 10BASE-T Ethernet Controller with SPI | Microchip

ENC28J60T/SS - 10Mbps SPI Ethernet Controller | Microchip

ENC424J600-I/ML 10/100 Ethernet Controller | Microchip

ENC424J600-I/PT - 10/100 Ethernet Controller | Microchip

ENC424J600T-I/ML - 10/100 Ethernet Controller | Microchip

ENC424J600T-I/PT - 10/100 Ethernet Controller | Microchip

EP1810GC-35 - UV PLD, 40ns, CMOS, CPGA68 | Altera / Rochester

EP1810GC-35AB - Classic EPLD, 48 Macrocells, 35ns | Altera

EP1810GI-45 - UV PLD, 50ns, 24 Macrocells, CPGA-68 | Altera

EP1810GM/883B - Classic EPLD 100MHz PGA-181 | Intel / Altera

EP1810GM883 - 48-Macrocell Classic EPLD, 5V, 68-Pin PGA | Altera

EP1810GM883B - 48-Macrocell EPLD, 5V CMOS, 883B Military | Altera

EP1810JC-25 - 48-Macrocell Classic EPLD, 25ns tPD | Intel

EP1810JC-35 - 48-Macrocell UV EPLD, 35ns, CQCC-68 | Intel / Altera

EP1810JC-45 - Classic EPLD, 48 Macrocells, 45ns, UV PLCC | Altera

EP1810JC35 - 48 Macrocell Classic EPLD 35ns CMOS PLCC-68 | Altera

EP1810JI-35 - 48-Macrocell Classic EPLD, 35ns | Intel / Altera

EP1810JI-45 - 48-Macrocell UV PLD, 33.3 MHz, 68-pin JLCC | Altera

EP1810JM-45 - 48 Macrocell Classic EPLD, 45ns, CMOS | Altera