2ED21084S06JXUMA1 vs 2ED21064S06JXUMA1 Comparison
Detailed side-by-side comparison of 2ED21084S06JXUMA1 by Infineon and 2ED21064S06JXUMA1 by Infineon. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Infineon
2ED21084S06JXUMA1 - 650V 0.7A Half-Bridge Gate Driver | Infineon
2ED21084S06JXUMA1 ✓ ActiveInfineon
2ED21064S06JXUMA1 - 650V 0.7A Half-Bridge Gate Driver | Infineon
2ED21064S06JXUMA1 ✓ ActiveSpecification Comparison
| Parameter | 2ED21084S06JXUMA1 | 2ED21064S06JXUMA1 |
|---|---|---|
| Brand | Infineon | Infineon |
| Category | Power MOSFET Drivers | Power MOSFET Drivers |
| Lifecycle Status | Active | Active |
| Function | Half-bridge gate driver | High-Side and Low-Side Gate Driver |
| Topology | Half-bridge (high-side + low-side) | High-Side, Low-Side with integrated bootstrap diode |
| High-side Offset Voltage (max) | 650 V | — |
| VCC Supply Voltage | 10 V to 20 V | — |
| Source Current (typical) | 0.29 A | 0.29 A |
| Sink Current (typical) | 0.7 A | 0.7 A |
| Propagation Delay Rise (typical) | 100 ns | — |
| Propagation Delay Fall (typical) | 35 ns | — |
| Input Logic | Non-inverting (HIN/LIN) | — |
| Bootstrap Diode | Integrated | Integrated |
| UVLO (VCC) | [DATA_NEEDED: VCC UVLO threshold] | — |
| UVLO (VBS) | [DATA_NEEDED: VBS UVLO threshold] | — |
| Operating Temperature | -40C to +125C | -40C to +125C |
| Package | PG-DSO-14-49 (14-pin wide-body SOIC) | PG-DSO-14 (14-pin SOIC) |
| Mounting Type | Surface Mount | Surface Mount |
| MSL Level | 3 | [DATA_NEEDED: MSL level] |
| RoHS Status | Compliant | ROHS3 Compliant |
| Configuration | — | Half-Bridge (2 outputs, non-inverting) |
| Maximum Offset / Boot Voltage | — | 650 V |
| Supply Voltage (VCC) | — | 10 V to 20 V |
| Rise Time (typical) | — | [DATA_NEEDED: rise time] |
| Fall Time (typical) | — | [DATA_NEEDED: fall time] |
| Propagation Delay (typical) | — | 100 ns |
| Channel-to-Channel Delay Match | — | [DATA_NEEDED: channel-to-channel delay match] |
| Under-Voltage Lockout | — | Yes (both channels) |
| Input Logic Compatibility | — | 3.3 V / 5 V CMOS |
| Negative Gate Drive Robustness | — | -0.7 V |