2ED21084S06JXUMA1 vs 2ED21064S06JXUMA1 Comparación
Comparación detallada lado a lado de 2ED21084S06JXUMA1 por Infineon y 2ED21064S06JXUMA1 por Infineon. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Infineon
2ED21084S06JXUMA1 - 650V 0.7A Half-Bridge Gate Driver | Infineon
2ED21084S06JXUMA1 ✓ ActivoInfineon
2ED21064S06JXUMA1 - 650V 0.7A Half-Bridge Gate Driver | Infineon
2ED21064S06JXUMA1 ✓ ActivoComparación de especificaciones
| Parámetro | 2ED21084S06JXUMA1 | 2ED21064S06JXUMA1 |
|---|---|---|
| Marca | Infineon | Infineon |
| Categoría | Power MOSFET Drivers | Power MOSFET Drivers |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,55 | $0,85 |
| Función | Half-bridge gate driver | High-Side and Low-Side Gate Driver |
| Topología | Half-bridge (high-side + low-side) | High-Side, Low-Side with integrated bootstrap diode |
| High-side Offset Voltage (max) | 650 V | — |
| VCC Supply Voltage | 10 V to 20 V | — |
| Source Current (typical) | 0.29 A | 0.29 A |
| Sink Current (typical) | 0.7 A | 0.7 A |
| Propagation Delay Rise (typical) | 100 ns | — |
| Propagation Delay Fall (typical) | 35 ns | — |
| Input Logic | Non-inverting (HIN/LIN) | — |
| Bootstrap Diode | Integrated | Integrated |
| UVLO (VCC) | [DATA_NEEDED: VCC UVLO threshold] | — |
| UVLO (VBS) | [DATA_NEEDED: VBS UVLO threshold] | — |
| Temperatura de funcionamiento | -40C to +125C | -40C to +125C |
| Encapsulado | PG-DSO-14-49 (14-pin wide-body SOIC) | PG-DSO-14 (14-pin SOIC) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Nivel MSL | 3 | [DATA_NEEDED: MSL level] |
| Estado RoHS | Compliant | ROHS3 Compliant |
| Configuration | — | Half-Bridge (2 outputs, non-inverting) |
| Maximum Offset / Boot Voltage | — | 650 V |
| Supply Voltage (VCC) | — | 10 V to 20 V |
| Rise Time (typical) | — | [DATA_NEEDED: rise time] |
| Fall Time (typical) | — | [DATA_NEEDED: fall time] |
| Propagation Delay (typical) | — | 100 ns |
| Channel-to-Channel Delay Match | — | [DATA_NEEDED: channel-to-channel delay match] |
| Under-Voltage Lockout | — | Yes (both channels) |
| Input Logic Compatibility | — | 3.3 V / 5 V CMOS |
| Negative Gate Drive Robustness | — | -0.7 V |