EP1810JC-35 vs EP1810JI-45 Comparison

Detailed side-by-side comparison of EP1810JC-35 by Intel and EP1810JI-45 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP1810JC-35 EP1810JI-45
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $5.48 $9.75
Device Family Classic EPLD (EP1810) —
Device Type UV-Erasable Complex PLD (UV PLD / CPLD) UV-Erasable / OTP Complex PLD
Number of Macrocells 48 —
Propagation Delay (tpd) 35 ns (max) —
Maximum Clock Frequency [DATA_NEEDED: fmax for this speed grade] —
Process Technology CMOS —
Supply Voltage (Vcc) 5 V (nominal) —
Maximum Supply Voltage 5.25 V (per distributor listing) —
Package Type CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) 68-pin JLCC (J-leaded ceramic chip carrier)
Number of Terminals 68 68
Terminal Form J-Bend J BEND
Operating Temperature Range 0°C to 70°C (Commercial) —
Temperature Grade Commercial INDUSTRIAL
Erasure Method UV (quartz-windowed ceramic package) —
RoHS Status Compliant (per Altera listing) —
Lead-Free Status Lead-free (per distributor listing) —
Mounting Type Surface Mount (J-Lead) —
Logic Architecture Programmable AND/OR array with macrocell outputs —
Manufacturer — Altera (now Intel FPGA)
Series — Classic EPLD Family
Macrocell Count — 48
Maximum Operating Frequency — 33.3 MHz
Propagation Delay (tPD) — 50 ns
Configurable I/O Lines — 48
Dedicated Inputs — 12
Technology — CMOS EPROM
Package Code — QCCJ
Package Shape — SQUARE
Operating Temperature — -40 °C to +85 °C
Supply Voltage — 5 V (TTL compatible)
Programming Method — UV-erase (windowed) / OTP via JEDEC

Datasheets & Resources

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