EP1810JC-35 vs EP1810JI-45 Comparación
Comparación detallada lado a lado de EP1810JC-35 por Intel y EP1810JI-45 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810JC-35 | EP1810JI-45 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $5,48 | $9,75 |
| Device Family | Classic EPLD (EP1810) | — |
| Device Type | UV-Erasable Complex PLD (UV PLD / CPLD) | UV-Erasable / OTP Complex PLD |
| Number of Macrocells | 48 | — |
| Propagation Delay (tpd) | 35 ns (max) | — |
| Frecuencia de reloj máxima | [DATA_NEEDED: fmax for this speed grade] | — |
| Process Technology | CMOS | — |
| Supply Voltage (Vcc) | 5 V (nominal) | — |
| Maximum Supply Voltage | 5.25 V (per distributor listing) | — |
| Package Type | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) | 68-pin JLCC (J-leaded ceramic chip carrier) |
| Number of Terminals | 68 | 68 |
| Terminal Form | J-Bend | J BEND |
| Rango de temperatura de funcionamiento | 0°C to 70°C (Commercial) | — |
| Temperature Grade | Commercial | INDUSTRIAL |
| Erasure Method | UV (quartz-windowed ceramic package) | — |
| Estado RoHS | Compliant (per Altera listing) | — |
| Lead-Free Status | Lead-free (per distributor listing) | — |
| Tipo de montaje | Surface Mount (J-Lead) | — |
| Logic Architecture | Programmable AND/OR array with macrocell outputs | — |
| Manufacturer | — | Altera (now Intel FPGA) |
| Series | — | Classic EPLD Family |
| Macrocell Count | — | 48 |
| Maximum Operating Frequency | — | 33.3 MHz |
| Propagation Delay (tPD) | — | 50 ns |
| Configurable I/O Lines | — | 48 |
| Dedicated Inputs | — | 12 |
| Technology | — | CMOS EPROM |
| Package Code | — | QCCJ |
| Package Shape | — | SQUARE |
| Temperatura de funcionamiento | — | -40 °C to +85 °C |
| Tensión de alimentación | — | 5 V (TTL compatible) |
| Programming Method | — | UV-erase (windowed) / OTP via JEDEC |