EP1810JC-35 vs EP1810JI-45 Vergleich

Detaillierter Direktvergleich von EP1810JC-35 von Intel und EP1810JI-45 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP1810JC-35 EP1810JI-45
Marke Intel Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $5,48 $9,75
Device Family Classic EPLD (EP1810) —
Device Type UV-Erasable Complex PLD (UV PLD / CPLD) UV-Erasable / OTP Complex PLD
Number of Macrocells 48 —
Propagation Delay (tpd) 35 ns (max) —
Maximale Taktfrequenz [DATA_NEEDED: fmax for this speed grade] —
Process Technology CMOS —
Supply Voltage (Vcc) 5 V (nominal) —
Maximum Supply Voltage 5.25 V (per distributor listing) —
Package Type CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) 68-pin JLCC (J-leaded ceramic chip carrier)
Number of Terminals 68 68
Terminal Form J-Bend J BEND
Betriebstemperaturbereich 0°C to 70°C (Commercial) —
Temperature Grade Commercial INDUSTRIAL
Erasure Method UV (quartz-windowed ceramic package) —
RoHS-Status Compliant (per Altera listing) —
Lead-Free Status Lead-free (per distributor listing) —
Montageart Surface Mount (J-Lead) —
Logic Architecture Programmable AND/OR array with macrocell outputs —
Manufacturer — Altera (now Intel FPGA)
Series — Classic EPLD Family
Macrocell Count — 48
Maximum Operating Frequency — 33.3 MHz
Propagation Delay (tPD) — 50 ns
Configurable I/O Lines — 48
Dedicated Inputs — 12
Technology — CMOS EPROM
Package Code — QCCJ
Package Shape — SQUARE
Betriebstemperatur — -40 °C to +85 °C
Versorgungsspannung — 5 V (TTL compatible)
Programming Method — UV-erase (windowed) / OTP via JEDEC

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