EP1810LC-25 vs EP1810LC-30 Comparison

Detailed side-by-side comparison of EP1810LC-25 by Altera and EP1810LC-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP1810LC-25 EP1810LC-30
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $8.40 $9.95
Product Family Altera Classic EPLD —
Part Number EP1810LC-25 —
Macrocells 48 48
Propagation Delay (tPD) 25 ns —
Dedicated Inputs 12 —
I/O Pins 48 —
External Clock Inputs 4 —
Supply Voltage (VCC) 5 V (TTL-compatible) —
Operating Mode Turbo-only (no slow-power mode) —
Package 68-pin JLCC (J-leaded ceramic chip carrier) JLCC-68 (68-pin J-Lead ceramic chip carrier)
Package Code LC = 68-pin JLCC —
Mounting Type Surface Mount —
Technology CMOS EPLD (erasable programmable logic device) CMOS, low-power (LC)
Programmable Interconnect Global + Local buses —
Programming Method Altera Classic programmer + MAX+PLUS II legacy flow —
Lifecycle Status Obsolete (legacy Altera Classic family) —
RoHS Status [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] unknown (legacy ceramic package)
Operating Temperature [DATA_NEEDED: temperature grade for LC package] [DATA_NEEDED: temperature grade]
Product Type — Classic EPLD (Erasable Programmable Logic Device)
Family — Altera Classic EPLD
Flip-Flops — 48 (one per macrocell)
Speed Grade (tPD) — 30 ns
Supply Voltage — 5 V (typical)
Programming — Device programmer or JTAG
Standby Current — [DATA_NEEDED: ICC standby]
Number of Pins — 68
Number of I/O Pins — [DATA_NEEDED: I/O count]
Logic Blocks — 48 macrocells

Datasheets & Resources

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