EP1810LC-25 vs EP1810LC-30 比較
詳細な並列比較: EP1810LC-25 メーカー: Altera および EP1810LC-30 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1810LC-25 | EP1810LC-30 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $8.40 | $9.95 |
| Product Family | Altera Classic EPLD | — |
| Part Number | EP1810LC-25 | — |
| Macrocells | 48 | 48 |
| Propagation Delay (tPD) | 25 ns | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 | — |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 5 V (TTL-compatible) | — |
| Operating Mode | Turbo-only (no slow-power mode) | — |
| パッケージ | 68-pin JLCC (J-leaded ceramic chip carrier) | JLCC-68 (68-pin J-Lead ceramic chip carrier) |
| Package Code | LC = 68-pin JLCC | — |
| 実装タイプ | Surface Mount | — |
| Technology | CMOS EPLD (erasable programmable logic device) | CMOS, low-power (LC) |
| Programmable Interconnect | Global + Local buses | — |
| Programming Method | Altera Classic programmer + MAX+PLUS II legacy flow | — |
| ライフサイクル状態 | Obsolete (legacy Altera Classic family) | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] | unknown (legacy ceramic package) |
| 動作温度 | [DATA_NEEDED: temperature grade for LC package] | [DATA_NEEDED: temperature grade] |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera Classic EPLD |
| Flip-Flops | — | 48 (one per macrocell) |
| Speed Grade (tPD) | — | 30 ns |
| 電源電圧 | — | 5 V (typical) |
| Programming | — | Device programmer or JTAG |
| Standby Current | — | [DATA_NEEDED: ICC standby] |
| ピン数 | — | 68 |
| Number of I/O Pins | — | [DATA_NEEDED: I/O count] |
| Logic Blocks | — | 48 macrocells |