EP1810LC-25 vs EP1810LC-35T Comparison

Detailed side-by-side comparison of EP1810LC-25 by Altera and EP1810LC-35T by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP1810LC-25 EP1810LC-35T
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $8.40 $115.20
Product Family Altera Classic EPLD —
Part Number EP1810LC-25 —
Macrocells 48 —
Propagation Delay (tPD) 25 ns —
Dedicated Inputs 12 —
I/O Pins 48 —
External Clock Inputs 4 —
Supply Voltage (VCC) 5 V (TTL-compatible) —
Operating Mode Turbo-only (no slow-power mode) —
Package 68-pin JLCC (J-leaded ceramic chip carrier) 68-pin PLCC (Plastic Leaded Chip Carrier)
Package Code LC = 68-pin JLCC —
Mounting Type Surface Mount Surface Mount (PLCC socket or direct solder)
Technology CMOS EPLD (erasable programmable logic device) CMOS
Programmable Interconnect Global + Local buses —
Programming Method Altera Classic programmer + MAX+PLUS II legacy flow UV-erasable (ceramic) / OTP (plastic); MAX+PLUS II
Lifecycle Status Obsolete (legacy Altera Classic family) —
RoHS Status [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] Non-compliant (legacy PLCC product)
Operating Temperature [DATA_NEEDED: temperature grade for LC package] 0 C to +70 C (Commercial)
Device Family — EP1810 Classic EPLD
Product Type — Erasable Programmable Logic Device (EPLD)
Usable Gates — 900
Macro Cells — 48
Pin-to-Pin Delay (tpd) — 35 ns
Maximum Frequency (fmax) — 28.6 MHz
Supply Voltage (Vcc) — 5 V
Logic Compatibility — 100% TTL emulation
Package Suffix — T = Tape and Reel
Logic Family Replacement Target — 74LS low-power Schottky TTL

Datasheets & Resources

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