EP1810LC-25 vs EP1810LC-35T Comparaison
Comparaison détaillée côte à côte de EP1810LC-25 par Altera et EP1810LC-35T par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1810LC-25 | EP1810LC-35T |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $8,40 | $115,20 |
| Product Family | Altera Classic EPLD | — |
| Part Number | EP1810LC-25 | — |
| Macrocells | 48 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 | — |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 5 V (TTL-compatible) | — |
| Operating Mode | Turbo-only (no slow-power mode) | — |
| Boîtier | 68-pin JLCC (J-leaded ceramic chip carrier) | 68-pin PLCC (Plastic Leaded Chip Carrier) |
| Package Code | LC = 68-pin JLCC | — |
| Type de montage | Surface Mount | Surface Mount (PLCC socket or direct solder) |
| Technology | CMOS EPLD (erasable programmable logic device) | CMOS |
| Programmable Interconnect | Global + Local buses | — |
| Programming Method | Altera Classic programmer + MAX+PLUS II legacy flow | UV-erasable (ceramic) / OTP (plastic); MAX+PLUS II |
| Statut du cycle de vie | Obsolete (legacy Altera Classic family) | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] | Non-compliant (legacy PLCC product) |
| Température de fonctionnement | [DATA_NEEDED: temperature grade for LC package] | 0 C to +70 C (Commercial) |
| Device Family | — | EP1810 Classic EPLD |
| Product Type | — | Erasable Programmable Logic Device (EPLD) |
| Usable Gates | — | 900 |
| Macro Cells | — | 48 |
| Pin-to-Pin Delay (tpd) | — | 35 ns |
| Maximum Frequency (fmax) | — | 28.6 MHz |
| Supply Voltage (Vcc) | — | 5 V |
| Logic Compatibility | — | 100% TTL emulation |
| Package Suffix | — | T = Tape and Reel |
| Logic Family Replacement Target | — | 74LS low-power Schottky TTL |