EP1810LC-25 vs EP1810LC-35T Vergleich

Detaillierter Direktvergleich von EP1810LC-25 von Altera und EP1810LC-35T von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP1810LC-25 EP1810LC-35T
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $8,40 $115,20
Product Family Altera Classic EPLD —
Part Number EP1810LC-25 —
Macrocells 48 —
Propagation Delay (tPD) 25 ns —
Dedicated Inputs 12 —
I/O Pins 48 —
External Clock Inputs 4 —
Supply Voltage (VCC) 5 V (TTL-compatible) —
Operating Mode Turbo-only (no slow-power mode) —
Gehäuse 68-pin JLCC (J-leaded ceramic chip carrier) 68-pin PLCC (Plastic Leaded Chip Carrier)
Package Code LC = 68-pin JLCC —
Montageart Surface Mount Surface Mount (PLCC socket or direct solder)
Technology CMOS EPLD (erasable programmable logic device) CMOS
Programmable Interconnect Global + Local buses —
Programming Method Altera Classic programmer + MAX+PLUS II legacy flow UV-erasable (ceramic) / OTP (plastic); MAX+PLUS II
Lebenszyklusstatus Obsolete (legacy Altera Classic family) —
RoHS-Status [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] Non-compliant (legacy PLCC product)
Betriebstemperatur [DATA_NEEDED: temperature grade for LC package] 0 C to +70 C (Commercial)
Device Family — EP1810 Classic EPLD
Product Type — Erasable Programmable Logic Device (EPLD)
Usable Gates — 900
Macro Cells — 48
Pin-to-Pin Delay (tpd) — 35 ns
Maximum Frequency (fmax) — 28.6 MHz
Supply Voltage (Vcc) — 5 V
Logic Compatibility — 100% TTL emulation
Package Suffix — T = Tape and Reel
Logic Family Replacement Target — 74LS low-power Schottky TTL

Datenblätter & Ressourcen

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