EP1810LC-25 vs EP1810LC-35T Comparação
Comparação detalhada lado a lado de EP1810LC-25 por Altera e EP1810LC-35T por Intel. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EP1810LC-25 | EP1810LC-35T |
|---|---|---|
| Marca | Altera | Intel |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $8,40 | $115,20 |
| Product Family | Altera Classic EPLD | — |
| Part Number | EP1810LC-25 | — |
| Macrocells | 48 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 | — |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 5 V (TTL-compatible) | — |
| Operating Mode | Turbo-only (no slow-power mode) | — |
| Encapsulamento | 68-pin JLCC (J-leaded ceramic chip carrier) | 68-pin PLCC (Plastic Leaded Chip Carrier) |
| Package Code | LC = 68-pin JLCC | — |
| Tipo de montagem | Surface Mount | Surface Mount (PLCC socket or direct solder) |
| Technology | CMOS EPLD (erasable programmable logic device) | CMOS |
| Programmable Interconnect | Global + Local buses | — |
| Programming Method | Altera Classic programmer + MAX+PLUS II legacy flow | UV-erasable (ceramic) / OTP (plastic); MAX+PLUS II |
| Status do ciclo de vida | Obsolete (legacy Altera Classic family) | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] | Non-compliant (legacy PLCC product) |
| Temperatura de operação | [DATA_NEEDED: temperature grade for LC package] | 0 C to +70 C (Commercial) |
| Device Family | — | EP1810 Classic EPLD |
| Product Type | — | Erasable Programmable Logic Device (EPLD) |
| Usable Gates | — | 900 |
| Macro Cells | — | 48 |
| Pin-to-Pin Delay (tpd) | — | 35 ns |
| Maximum Frequency (fmax) | — | 28.6 MHz |
| Supply Voltage (Vcc) | — | 5 V |
| Logic Compatibility | — | 100% TTL emulation |
| Package Suffix | — | T = Tape and Reel |
| Logic Family Replacement Target | — | 74LS low-power Schottky TTL |