EP1810LC-25T vs EP1810JC35 Comparison
Detailed side-by-side comparison of EP1810LC-25T by Intel and EP1810JC35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP1810LC-25T | EP1810JC35 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.40 | $9.75 |
| Family | Altera Classic EP1810 | Altera Classic EPLD |
| Device Type | EPLD (Erasable/OTP Complex PLD) | — |
| Macrocells | 48 (4 quadrants x 12 macrocells) | 48 |
| Usable Gates | Approx. 900 | — |
| Dedicated Inputs | 16 | — |
| Bidirectional I/O Pins | 48 | — |
| External Clocks | 4 | — |
| Propagation Delay (tPD) | 25 ns | 35 ns |
| Supply Voltage (VCC) | 5 V nominal | — |
| Operating Temperature | 0 °C to +70 °C (commercial) | 0 C to +70 C (Commercial) |
| Package | 28-pin J-lead PLCC (Plastic Leaded Chip Carrier) | PLCC-68 (J-lead, ceramic) |
| Mounting Type | Surface Mount | — |
| Technology | CMOS, UV-erasable / OTP | — |
| I/O Standard | TTL-compatible 5 V | — |
| RoHS Status | [DATA_NEEDED: RoHS status - confirm with manufacturer] | [DATA_NEEDED: RoHS compliance for EP1810JC35] |
| Programming Tool | Altera MAX+PLUS II / Quartus Classic | — |
| Product Type | — | UV-erasable / OTP Complex PLD (EPLD) |
| Logic Gates (typ.) | — | [DATA_NEEDED: logic gates count] |
| Maximum User I/O Pins | — | [DATA_NEEDED: user I/O count for PLCC-68] |
| Maximum Clock Frequency | — | 40 MHz |
| Supply Voltage (VCC max) | — | 5.25 V |
| Supply Voltage (VCC min) | — | [DATA_NEEDED: VCC minimum] |
| Process Technology | — | CMOS EPROM cell |
| Package Code | — | QCCJ |
| Terminal Form | — | J-BEND |
| Number of Terminals | — | 68 |
| Programming | — | UV-erase (windowed) or OTP |
| Development Tool | — | Altera MAX+plus II / A+plus |