EP1810LC-25T vs EP1810JC35 对比
详细并排对比 EP1810LC-25T 出自 Intel 和 EP1810JC35 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1810LC-25T | EP1810JC35 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $8.40 | $9.75 |
| Family | Altera Classic EP1810 | Altera Classic EPLD |
| Device Type | EPLD (Erasable/OTP Complex PLD) | — |
| Macrocells | 48 (4 quadrants x 12 macrocells) | 48 |
| Usable Gates | Approx. 900 | — |
| Dedicated Inputs | 16 | — |
| Bidirectional I/O Pins | 48 | — |
| External Clocks | 4 | — |
| Propagation Delay (tPD) | 25 ns | 35 ns |
| Supply Voltage (VCC) | 5 V nominal | — |
| 工作温度 | 0 °C to +70 °C (commercial) | 0 C to +70 C (Commercial) |
| 封装 | 28-pin J-lead PLCC (Plastic Leaded Chip Carrier) | PLCC-68 (J-lead, ceramic) |
| 安装类型 | Surface Mount | — |
| Technology | CMOS, UV-erasable / OTP | — |
| I/O Standard | TTL-compatible 5 V | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status - confirm with manufacturer] | [DATA_NEEDED: RoHS compliance for EP1810JC35] |
| Programming Tool | Altera MAX+PLUS II / Quartus Classic | — |
| Product Type | — | UV-erasable / OTP Complex PLD (EPLD) |
| Logic Gates (typ.) | — | [DATA_NEEDED: logic gates count] |
| Maximum User I/O Pins | — | [DATA_NEEDED: user I/O count for PLCC-68] |
| 最大时钟频率 | — | 40 MHz |
| Supply Voltage (VCC max) | — | 5.25 V |
| Supply Voltage (VCC min) | — | [DATA_NEEDED: VCC minimum] |
| Process Technology | — | CMOS EPROM cell |
| Package Code | — | QCCJ |
| Terminal Form | — | J-BEND |
| Number of Terminals | — | 68 |
| Programming | — | UV-erase (windowed) or OTP |
| Development Tool | — | Altera MAX+plus II / A+plus |