EP1M350F780C7 vs EP1M350F780I5 Comparison
Detailed side-by-side comparison of EP1M350F780C7 by Intel and EP1M350F780I5 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP1M350F780I5 - Altera Mercury Enhanced Configuration Device, 780-pin FBGA | Intel
EP1M350F780I5 NrndSpecification Comparison
| Parameter | EP1M350F780C7 | EP1M350F780I5 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $162.00 | $178.00 |
| Family | Mercury (PLD) | β |
| Device Logic Elements | [DATA_NEEDED: exact LE count] | β |
| Logic Array Blocks (LABs) | 1440 | β |
| System Gates | 350,000 | β |
| Maximum User I/Os | 486 | β |
| Package | 780-ball FineLine BGA (F780) | 780-ball FineLine BGA (F780) |
| Package Type | FINE LINE BGA-780 | β |
| Supply Voltage (Core) | 1.8 V | β |
| Logic Family | CMOS | β |
| Operating Temperature | 0 C to 85 C (Commercial) | β |
| Mounting Type | Surface Mount | β |
| Transceivers / CDR Support | Up to 1.25 Gbps with CDR | β |
| Configuration Method | JTAG / Quartus II | β |
| RoHS Status | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status] |
| MSL Level | [DATA_NEEDED: MSL rating] | β |
| Process Technology | CMOS SRAM-based | β |
| Device Family | β | Altera Mercury (EP1M) Enhanced Configuration Device |
| Function | β | FPGA configuration PROM with integrated controller |
| Storage Density Code | β | 350 (high-density) |
| Supported Configuration Schemes | β | Passive Serial, Active Serial, Fast Passive Parallel |
| Internal Architecture | β | Configuration controller + flash memory array |
| Programming Method | β | In-system programmable via Altera Quartus / JTAG |
| Temperature Grade (suffix "I") | β | Industrial |
| Speed Grade | β | 5 |
| Target FPGA Compatibility | β | Altera APEX 20K, APEX II, Mercury, Stratix-class high-density FPGAs |
| JTAG Support | β | Yes (IEEE 1149.1 boundary scan) |
| Cascade / Multi-FPGA Support | β | Yes, supports daisy-chained multi-FPGA boot |
| Read-Back | β | Yes |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |