EP20K400BI652-2V vs EP20K400CB652C9ES 比較

詳細並排比較 EP20K400BI652-2V 由 Intel 與 EP20K400CB652C9ES 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP20K400BI652-2V EP20K400CB652C9ES
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete NRND
Family APEX 20K APEX 20KC
Series APEX 20K (EPLD-based SOPC) APEX 20KC
System Gates 400,000 —
Logic Elements 16,640 —
Maximum User I/O 502 —
Embedded Memory (bits) 212,992 —
Embedded Memory Blocks ESBs (Embedded System Blocks) —
Macros (per Mouser listing) 1664 —
Logic Family CMOS —
Process Technology 0.22 μm 0.15 µm CMOS
Core Supply Voltage (VCCINT) 2.5 V —
Propagation Delay 2.5 ns (typical) —
Internal Performance 200 MHz (speed grade -2) —
工作溫度 0 °C to +85 °C (industrial, "I") —
封裝 652-ball FineLine BGA (35 × 35 mm, 1.27 mm pitch) —
安裝類型 Surface Mount (BGA) Surface Mount
RoHS 狀態 [DATA_NEEDED: rohs_status] [DATA_NEEDED: RoHS status]
Configuration Interface JTAG (IEEE 1149.1) / Passive Serial —
Logic Elements / Cells — 16640
Total System Gates — 400000
Embedded Memory (Bits) — 212992
Number of User I/O — 488
Number of LABs/CLBs — [DATA_NEEDED: LAB count]
Number of Logic Array Blocks — 1040
Maximum Operating Frequency — 250 MHz
Core Voltage — 1.8 V
工作溫度範圍 — 0°C to +85°C (Commercial)
封裝 / 外殼 — 652-BGA
MSL 等級 — 3 (168 Hours)
Packaging — Tray
Programmability Type — In-system programmable (SRAM-based)
I/O Standards Supported — LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL
JTAG (IEEE 1149.1) — Yes
PLL — Yes (4-phase)

資料表與資源

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