EP20K400FC672-3X vs EP20K400FC672-3 Comparison
Detailed side-by-side comparison of EP20K400FC672-3X by Altera and EP20K400FC672-3 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K400FC672-3X - APEX 20K 400K Gates FPGA, 672-BGA | Altera
EP20K400FC672-3X ⚠ Last Time BuySpecification Comparison
| Parameter | EP20K400FC672-3X | EP20K400FC672-3 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last Time Buy | Obsolete |
| Logic Family | APEX 20K | CMOS, SRAM-based |
| Device Sub-family | EP20K400 | — |
| Technology | CMOS 0.22 µm | — |
| Number of Gates | 400,000 (typical) | — |
| Logic Cells | 16,640 | — |
| Macros / Macrocells | 1664 | — |
| User I/Os | 502 | — |
| Dedicated I/O Lines | 496 | — |
| Core Supply Voltage | 2.5 V | 2.5 V |
| Maximum Clock Frequency | 181.82 MHz | — |
| Typical Propagation Delay | 2.07 ns | — |
| Operating Temperature | 0 °C to 85 °C (commercial) | 0 °C to 85 °C |
| Speed Grade | -3X | -3 (commercial fastest) |
| Package | 672-ball FC-FBGA (Fine-pitch Chip-Scale BGA) | 672-pin FC-FBGA |
| Architecture | MultiCore (LUT + embedded CAM/RAM) | MultiCore (LUT + Embedded System Blocks) |
| Programming Interface | JTAG (IEEE 1149.1) / ByteBlaster / MasterBlaster | — |
| Mounting Type | Surface Mount (BGA) | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Family | — | APEX 20K |
| Device Logic Elements | — | 16,640 cells |
| Typical Gate Count | — | 400,000 system gates |
| Maximum User I/Os | — | 502 |
| Propagation Delay | — | 2.5 ns |
| Internal Performance | — | 167 MHz |
| Process Technology | — | 0.22 µm CMOS |
| Package Code | — | BGA |
| Number of Terminals | — | 672 |
| Terminal Form | — | Ball (BGA) |
| Programming Method | — | SRAM, JTAG (ByteBlaster) |
| Lifecycle Status | — | Obsolete / Legacy |