EP20K400FC672-3X vs EP20K400FC672-3 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400FC672-3X sa pamamagitan ng Altera at EP20K400FC672-3 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EP20K400FC672-3X EP20K400FC672-3X - APEX 20K 400K Gates FPGA, 672-BGA | Altera

EP20K400FC672-3X - APEX 20K 400K Gates FPGA, 672-BGA | Altera

EP20K400FC672-3X ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EP20K400FC672-3X EP20K400FC672-3
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili Obsolete
Logic Family APEX 20K CMOS, SRAM-based
Device Sub-family EP20K400 —
Technology CMOS 0.22 µm —
Number of Gates 400,000 (typical) —
Logic Cells 16,640 —
Macros / Macrocells 1664 —
User I/Os 502 —
Dedicated I/O Lines 496 —
Core Supply Voltage 2.5 V 2.5 V
Maksimum na Taktiko ng Oras 181.82 MHz —
Typical Propagation Delay 2.07 ns —
Temperature na Operasyon 0 °C to 85 °C (commercial) 0 °C to 85 °C
Speed Grade -3X -3 (commercial fastest)
Packhaging 672-ball FC-FBGA (Fine-pitch Chip-Scale BGA) 672-pin FC-FBGA
Architecture MultiCore (LUT + embedded CAM/RAM) MultiCore (LUT + Embedded System Blocks)
Programming Interface JTAG (IEEE 1149.1) / ByteBlaster / MasterBlaster —
Uri ng Pagpapasok Surface Mount (BGA) Surface Mount
Tindminan RoHS [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status]
Family — APEX 20K
Device Logic Elements — 16,640 cells
Typical Gate Count — 400,000 system gates
Maximum User I/Os — 502
Propagation Delay — 2.5 ns
Internal Performance — 167 MHz
Process Technology — 0.22 µm CMOS
Package Code — BGA
Number of Terminals — 672
Terminal Form — Ball (BGA)
Programming Method — SRAM, JTAG (ByteBlaster)
Katayuan ng Lifecycle — Obsolete / Legacy

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