EP20K400FC672-3X vs EP20K400FC672-3 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP20K400FC672-3X disebabkan oleh Altera dan EP20K400FC672-3 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Altera
EP20K400FC672-3X EP20K400FC672-3X - APEX 20K 400K Gates FPGA, 672-BGA | Altera

EP20K400FC672-3X - APEX 20K 400K Gates FPGA, 672-BGA | Altera

EP20K400FC672-3X ⚠ Bahagian terakhir untuk beli

Pengandingan Spesifikasi

Parametr EP20K400FC672-3X EP20K400FC672-3
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Masa Terakhir Dibeli Obsolete
Logic Family APEX 20K CMOS, SRAM-based
Device Sub-family EP20K400 —
Technology CMOS 0.22 µm —
Number of Gates 400,000 (typical) —
Logic Cells 16,640 —
Macros / Macrocells 1664 —
User I/Os 502 —
Dedicated I/O Lines 496 —
Core Supply Voltage 2.5 V 2.5 V
Frekuensi Klock Maksimum 181.82 MHz —
Typical Propagation Delay 2.07 ns —
Suhu Operasi 0 °C to 85 °C (commercial) 0 °C to 85 °C
Speed Grade -3X -3 (commercial fastest)
Kemasan 672-ball FC-FBGA (Fine-pitch Chip-Scale BGA) 672-pin FC-FBGA
Architecture MultiCore (LUT + embedded CAM/RAM) MultiCore (LUT + Embedded System Blocks)
Programming Interface JTAG (IEEE 1149.1) / ByteBlaster / MasterBlaster —
Jenis Pemasangan Surface Mount (BGA) Surface Mount
Status RoHS [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status]
Family — APEX 20K
Device Logic Elements — 16,640 cells
Typical Gate Count — 400,000 system gates
Maximum User I/Os — 502
Propagation Delay — 2.5 ns
Internal Performance — 167 MHz
Process Technology — 0.22 µm CMOS
Package Code — BGA
Number of Terminals — 672
Terminal Form — Ball (BGA)
Programming Method — SRAM, JTAG (ByteBlaster)
Status Lingkungan Hidup — Obsolete / Legacy

Laporan Datasheet & Sumber

Lihat Semua Produk Buat BOQ Minta Bao Harga