EP20K400GC655-1X vs EP20K400GC655-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400GC655-1X sa pamamagitan ng Altera at EP20K400GC655-1 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 ObsoletePagsanggunian na paghahambing
| Parametro | EP20K400GC655-1X | EP20K400GC655-1 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Family | Altera APEX 20K | — |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Technology | CMOS | — |
| Gate Count | 400K gates | — |
| Logic Elements | 16640 cells | 16,640 |
| Maximum System Frequency | 250 MHz | — |
| Propagation Delay | 2.5 ns | 2.5 ns |
| Core Supply Voltage | 2.5 V | 2.5 V |
| I/O Supply Voltage | 2.5 V / 3.3 V | 3.3 V |
| Number of User I/O | 496 | — |
| Number of Dedicated Inputs | 6 | — |
| Number of Terminals | 655 | — |
| Package Type | CPGA-655 (Ceramic Pin Grid Array) | — |
| Package Body Material | Ceramic | — |
| Process Technology | 0.22 um | 0.22 µm CMOS |
| Hanay ng Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | — |
| Embedded RAM Bits | [DATA_NEEDED: embedded RAM bits] | — |
| Tindminan RoHS | unknown | Non-compliant (contains lead in ceramic package) |
| Family | — | APEX 20K |
| Series | — | EP20K400 |
| Maximum Gates | — | 1,052,000 |
| Typical Gates | — | 400,000 |
| Embedded System Blocks (ESBs) | — | 4 |
| Total RAM Bits | — | 212,992 |
| Maximum User I/O | — | 502 |
| Dedicated Inputs | — | 6 |
| Maximum Internal Frequency | — | 250 MHz |
| Packhaging | — | 655-pin CPGA (Ceramic Pin Grid Array) |
| Bilang ng Pin | — | 655 |
| Uri ng Pagpapasok | — | Through-Hole |
| Temperature na Operasyon | — | 0 °C to +85 °C (commercial) |
| Configuration Modes | — | Passive Serial, Passive Parallel Async, Passive Parallel Sync |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |